Abstract: In an embodiment, a method of providing quality of service (QoS) to at least one resource of a hardware processor includes providing, in a memory of the hardware processor, a context including at least one quality of service parameter and allocating access to the at least one resource of the hardware processor based on the quality of service parameter of the context, a device identifier, a virtual machine identifier, and the context.

Abstract: In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.

Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.

Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.

Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.

Abstract: In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.

Abstract: In an embodiment, a method of providing quality of service (QoS) to at least one resource of a hardware processor includes providing, in a memory of the hardware processor, a context including at least one quality of service parameter and allocating access to the at least one resource of the hardware processor based on the quality of service parameter of the context, a device identifier, a virtual machine identifier, and the context.

Abstract: In an embodiment, a method include, in a hardware processor, producing, by a block of hardware logic resources, a constrained randomly generated or pseudo-randomly generated number (CRGN) based on a bit mask stored in a register memory.

Abstract: In an embodiment, interfacing a pipeline with two or more interfaces in a hardware processor includes providing a single pipeline in a hardware processor. The single pipeline presents at least two visible units. The single pipeline includes replicated architecturally visible structures, shared logic resources, and shared architecturally hidden structures. The method further includes receiving a request from one of a plurality of interfaces at one of the visible units. The method also includes tagging the request with an identifier based on the one of the at least two visible units that received the request. The method further includes processing the request in the single pipeline by propagating the request through the single pipeline through the replicated architecturally visible structures that correspond with the identifier.

Abstract: An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.