Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

Abstract: Methods and apparatus to optically couple an optoelectronic chip to a waveguide are disclosed. A disclosed apparatus includes a substrate, a waveguide mounted on the substrate and an optoelectronic chip bonded to the substrate and having an optical element directly engaging the waveguide.

Abstract: An apparatus comprising a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, a die including an optical area, the die being flip-chip bonded to the substrate, and an optical inter-connector optically coupled to the optical area and at least partially positioned between the die and the base substrate, the optical inter-connector positioned in a trench formed in the solder resist layer and the conductive layer. A process comprising providing a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, forming a trench in the conductive layer and the solder resist layer, positioning a waveguide in the trench, and flip-chip bonding a die to the substrate, the die including an optical area, such that the optical area is optically coupled to the waveguide.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: Methods and apparatuses for wafer support and release using sacrificial materials in wafer processing. In one embodiment, a solution of a sacrificial polymer is spray-coated on the wafer bump side to form a thin layer of the sacrificial polymer after solvent vaporization. An adhesive layer is then used to attach the wafer bump side onto a wafer support substrate over the sacrificial polymer to support the wafer in backside processing. After wafer thinning and backside metal deposition, the wafer is exposed to heat to thermally decompose the sacrificial polymer into gases. The decomposition of the sacrificial polymer reduces the adhesion of the adhesive layer to the bump side of the wafer such that, when the support substrate is detached from the wafer, the adhesive layer is detached together with the support substrate from the wafer bump side, leaving almost no residual traces.

Abstract: An apparatus comprising a substrate having a trench therein, the trench extending to an edge of the substrate, a waveguide array positioned in the trench, the waveguide array extending to the edge of the substrate, and a ferrule attached at or near the edge of the substrate and spanning a width of the waveguide array, the ferrule being directly in contact with a surface of the waveguide array. A process comprising positioning a waveguide in a trench on a substrate, the waveguide extending to an edge of the substrate, and attaching a ferrule at or near the edge of the substrate, the ferrule including a recess having a bottom, wherein the bottom is in direct contact with a surface of the waveguide.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to the clock source. The metal layer is embedded in dielectric layers made of thick film using a wafer-level thick film (WLTF) process.

Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.

Abstract: In one embodiment there is provided a method comprising performing a sawing operation on a wafer; and treating the wafer to at least reduce a propagation of micro-cracks formed in the wafer during the sawing. In another embodiment there is provided a semi-conductor die comprising a substrate having a central first portion, and a peripheral second portion around the central first portion; an integrated circuit formed on the central first portion; and a guard ring disposed between the first and second portions of the substrate to prevent a propagation of cracks found in that second portion to the first portion, wherein the second portion includes micro-cracks filled with a crack-healing material to arrest propagation of the micro-cracks beyond the guard ring and into the central first portion.

Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The process flow may include forming an inter-layer dielectric with spray coating or lamination over a surface with high aspect ratio structures.

Abstract: An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to the clock source. The metal layer is embedded in dielectric layers made of thick film using a wafer-level thick film (WLTF) process.

Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.

Abstract: In one embodiment there is provided a method comprising performing a singulation operation on a wafer; and treating the wafer to at least reduce a propagation of micro-cracks formed in the wafer during the singulation. In another embodiment there is provided a semi-conductor die comprising a substrate having a central first portion, and a peripheral second portion around the central first portion; an integrated circuit formed on the central first portion; and a guard ring disposed between the first and second portions of the substrate to prevent a propagation of micro-cracks formed in the second portion into the first portion, the micro-cracks having been formed during a singulation operation to separate the semiconductor die from a wafer, wherein the second portion includes micro-cracks filled with a crack-healing material to arrest propagation of the micro-cracks beyond the ring and into the central first portion.

Abstract: The adhesion of low k poly(arylene ether) dielectric coating compositions is effectively enhanced by a polycarbosilane promoter additive or primer. A coating composition is prepared by (a) providing a poly(arylene ether) composition; and (b) adding to said composition a small effective adhesion promoting amount of certain polycarbosilanes. The adhesion enhanced coating compositions are cured by heat treatment at temperatures in excess of 50° C. to form a polycarbosilane-modified poly(arylene ether) polymer composition having a low k dielectric constant for use in semiconductor devices.

Abstract: The adhesion of low k poly(arylene ether) dielectric coating compositions is effectively enhanced by a polycarbosilane promoter additive or primer. A coating composition is prepared by (a) providing a poly(arylene ether) composition; and (b) adding to said composition a small effective adhesion promoting amount of certain polycarbosilanes. The adhesion enhanced coating compositions are cured by heat treatment at temperatures in excess of 50° C. to form a polycarbosilane-modified poly(arylene ether) polymer composition having a low k dielectric constant for use in semiconductor devices.

Abstract: In one embodiment there is provided a method comprising performing a sawing operation on a wafer; and treating the wafer to at least reduce a propagation of micro-cracks formed in the wafer during the sawing. In another embodiment there is provided a semi-conductor die comprising a substrate having a central first portion, and a peripheral second portion around the central first portion; an integrated circuit formed on the central first portion; and a guard ring disposed between the first and second portions of the substrate to prevent a propagation of cracks found in that second portion to the first portion, wherein the second portion includes micro-cracks filled with a crack-healing material to arrest propagation of the micro-cracks beyond the guard ring and into the central first portion.

Abstract: The adhesion of low k poly(arylene ether) dielectric coating compositions is effectively enhanced by a polycarbosilane promoter additive or primer. A coating composition is prepared by (a) providing a poly(arylene ether) composition; and (b) adding to said composition a small effective adhesion promoting amount of certain polycarbosilanes. The adhesion enhanced coating compositions are cured by heat treatment at temperatures in excess of 50° C. to form a polycarbosilane-modified poly(arylene ether) polymer composition having a low k dielectric constant for use in semiconductor devices.

Abstract: A method for cleaning the surface of a semiconductor wafer having an organic dielectric film thereon by removing residual slurry particles adhered to the wafer surface after chemical-mechanical planarization is provided. The semiconductor is subjected to a post CMP cleaning step by applying mechanical frictional force to the surface of the wafer while concurrently applying to the wafer surface and aqueous solution having a pH of greater than 10 for a period of time sufficient to wet and clean the wafer surface, the basic aqueous solution comprised of a surfactant and a tetra alkyl quaternary ammonium hydroxide compound such as tetramethylammonium hydroxide.