Patents by Inventor Anna M. George, legal representative

Anna M. George, legal representative has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7589417
    Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: September 15, 2009
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Gregory M. Chrysler, Steven N. Towle, Anna M. George, legal representative
  • Patent number: 7372120
    Abstract: Methods and apparatus to optically couple an optoelectronic chip to a waveguide are disclosed. A disclosed apparatus includes a substrate, a waveguide mounted on the substrate and an optoelectronic chip bonded to the substrate and having an optical element directly engaging the waveguide.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventors: Anna M. George, legal representative, Daoqiang Lu, Henning Braunisch, Gilroy Vandentop, Steven Towle
  • Patent number: 7369718
    Abstract: An apparatus comprising a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, a die including an optical area, the die being flip-chip bonded to the substrate, and an optical inter-connector optically coupled to the optical area and at least partially positioned between the die and the base substrate, the optical inter-connector positioned in a trench formed in the solder resist layer and the conductive layer. A process comprising providing a substrate comprising a base substrate, a conductive layer on the base substrate, and a solder resist layer on the conductive layer, forming a trench in the conductive layer and the solder resist layer, positioning a waveguide in the trench, and flip-chip bonding a die to the substrate, the die including an optical area, such that the optical area is optically coupled to the waveguide.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: May 6, 2008
    Assignee: Intel Corporation
    Inventors: Anna M. George, legal representative, Steven Towle
  • Patent number: 7256059
    Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.
    Type: Grant
    Filed: January 14, 2005
    Date of Patent: August 14, 2007
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Anna M. George, legal representative, Steven Towle, deceased
  • Patent number: 7226812
    Abstract: Methods and apparatuses for wafer support and release using sacrificial materials in wafer processing. In one embodiment, a solution of a sacrificial polymer is spray-coated on the wafer bump side to form a thin layer of the sacrificial polymer after solvent vaporization. An adhesive layer is then used to attach the wafer bump side onto a wafer support substrate over the sacrificial polymer to support the wafer in backside processing. After wafer thinning and backside metal deposition, the wafer is exposed to heat to thermally decompose the sacrificial polymer into gases. The decomposition of the sacrificial polymer reduces the adhesion of the adhesive layer to the bump side of the wafer such that, when the support substrate is detached from the wafer, the adhesive layer is detached together with the support substrate from the wafer bump side, leaving almost no residual traces.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: June 5, 2007
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Anna M. George, legal representative, Steven Towle, deceased
  • Patent number: 7177504
    Abstract: An apparatus comprising a substrate having a trench therein, the trench extending to an edge of the substrate, a waveguide array positioned in the trench, the waveguide array extending to the edge of the substrate, and a ferrule attached at or near the edge of the substrate and spanning a width of the waveguide array, the ferrule being directly in contact with a surface of the waveguide array. A process comprising positioning a waveguide in a trench on a substrate, the waveguide extending to an edge of the substrate, and attaching a ferrule at or near the edge of the substrate, the ferrule including a recess having a bottom, wherein the bottom is in direct contact with a surface of the waveguide.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Anna M. George, legal representative, Daoqiang Lu, Henning Braunisch, Steven Towle, deceased
  • Patent number: 7042106
    Abstract: The application discloses an apparatus comprising an optical die flip-chip bonded to a substrate and defining a volume between the optical die and the substrate, the optical die including an optically active area on a surface of the die facing the substrate, an optically transparent material occupying at least those portions of the volume substantially corresponding with the optically active area, and an underfill material occupying portions of the volume not occupied by the optically transparent material.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventors: Daoqiang Lu, Anna M. George, legal representative, Steven Towle, deceased
  • Patent number: 7012015
    Abstract: An embodiment of the present invention is a technique to distribute clock. At least a metal layer is formed to have a standing-wave structure to distribute a clock signal to receiver end points from a clock source such that the receiver end points are substantially electrically equivalent with respect to the clock source. The metal layer is embedded in dielectric layers made of thick film using a wafer-level thick film (WLTF) process.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: March 14, 2006
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Anna M. George, legal representative, Steven N. Towle, deceased
  • Patent number: 6977435
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: December 20, 2005
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, Bob Martell, Dave Ayers, R. Scott List, Peter Moon, Anna M. George, legal representative, Steven Towle, deceased