Patents by Inventor Anna M. Minvielle

Anna M. Minvielle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8309457
    Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
    Type: Grant
    Filed: October 27, 2011
    Date of Patent: November 13, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
  • Publication number: 20120045888
    Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
    Type: Application
    Filed: October 27, 2011
    Publication date: February 23, 2012
    Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
  • Patent number: 8048797
    Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
    Type: Grant
    Filed: May 19, 2009
    Date of Patent: November 1, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
  • Publication number: 20100009536
    Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
    Type: Application
    Filed: May 19, 2009
    Publication date: January 14, 2010
    Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
  • Patent number: 7538026
    Abstract: A method utilizing a multilayer anti-reflective coating layer structure can achieve low reflectivity at high numerical apertures. The multilayer anti-reflective coating structure can be utilized as a hard mask forming various integrated circuit structures. A multilayer anti-reflective coating structure can be utilized to form gate stacks comprised of polysilicon and a dielectric layer. A photoresist is applied above the multilayer anti-reflective coating which can include silicon oxynitride (SiON) and silicon rich nitride (SiRN).
    Type: Grant
    Filed: April 4, 2005
    Date of Patent: May 26, 2009
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kouros Ghandehari, Anna M. Minvielle, Marina V. Plat, Hirokazu Tokuno
  • Patent number: 7427457
    Abstract: The present invention discloses a system and method for designing grating structures for use in situ scatterometry during the photolithography process to detect a photoresist defect (e.g., photoresist erosion, pattern collapse or pattern bending). In one embodiment, a grating structure may be designed with a pitch or critical dimensional smaller than the one used for the semiconductor device. The pitch and the critical dimension of the grating structure may be varied. In another embodiment, the present invention provides for a feedback mechanism between the in situ scatterometry process and the photolithography process to provide an early warning of the existence of a photoresist defect. If a defect is detected on the wafer, the wafer may be sent to be re-worked or re-patterned, thereby avoiding scrapping the entire wafer.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: September 23, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Marina V. Plat, Calvin T. Gabriel, Christopher F. Lyons, Anna M. Minvielle
  • Patent number: 7384725
    Abstract: A method of forming a plurality of contact holes of varying pitch and density in a contact layer of an integrated circuit device is provided. The plurality of contact holes can include a plurality of regularly spaced contact holes having a first pitch along a first direction and a plurality of semi-isolated contact holes having a second pitch along a second direction. A double-dipole illumination source can transmit light energy through a mask having a pattern corresponding to a desired contact hole pattern. The double-dipole illumination source can include a first dipole aperture, which is oriented and optimized for patterning the regularly spaced contact holes, and a second dipole aperture, which is oriented substantially orthogonal to the first dipole aperture and optimized for patterning the plurality of semi-isolated contact holes. The contact layer can be etched using the patterned photoresist layer.
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: June 10, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anna M. Minvielle, Cyrus E. Tabery, Hung-eil Kim, Jongwook Kye
  • Patent number: 6255125
    Abstract: Prior to entering into manufacturing of a final production wafer, a series of test wafers are produced to analyze and test various structures. Each of the test wafers include a substrate, an insulating layer overlying the substrate, and a semi-conductive film layer formed over the insulating layer. The film layer is comprised of, for example, poly-silicon and has a predetermined thickness which substantially corresponds to the thickness of a film layer deposited on the final production wafer. The film layer is etched to form a desired pattern of structures and implanted with a dopant to diffuse dopant atoms thoughout. Thereafter, critical dimension measurements of the structures are taken preferably using electrical line width measurements techniques.
    Type: Grant
    Filed: March 26, 1999
    Date of Patent: July 3, 2001
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Regina T. Schmidt, Christopher A. Spence, Anna M. Minvielle, Marina V. Plat, Khanh B. Nguyen
  • Patent number: 5985498
    Abstract: A method of characterizing linewidth errors in a lithography system 30 used to delineate a desired pattern onto an exposure site of a wafer 32. The pattern of a reticle 34 is transferred onto an exposure site 56 of a wafer 32 by projecting a slit of light extending in a slit direction y through the reticle while scanning the reticle and the wafer in a scanning direction x relative to the lens. The exposure site 56 is conceptually divided into a grid having one series of lines extending in the scan direction x and another series of lines extending in the slit direction y whereby points corresponding to perpendicular intersections of the lines may each be assigned a pair of coordinates (x,y). The linewidths of the pattern are measured for each of the points (x,y) and a linewidth error value ERROR (x,y) is generated for each of the points (x,y). An ERROR.sub.optical (y) value for each y coordinate is calculated by averaging the ERROR (x,y) values for each group of points (x,y) having a common y coordinate.
    Type: Grant
    Filed: March 1, 1999
    Date of Patent: November 16, 1999
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Harry Levinson, Khanh B. Nguyen, Anna M. Minvielle