Abstract: A short power signal path integrated circuit package placed on a printed circuit (PC) board and having a first dielectric layer. On top of this first dielectric layer a metallized die pad and a first metal ring, surrounding this metallized die pad, are positioned. The metallized die pad and the first metal ring electrically couple to the PC board to receive respectively a first power supply signal and a second power supply signal. An integrated circuit die is then affixed to the metallized die pad. This integrated circuit die has a first power supply signal bond pad and a second power supply signal bond pad, which respectively are coupled to the metallized die pad and the first metal ring. Consequently, the metallized die pad and the first metal ring operate as a first power supply plane and a second power supply plane coupling the first and the second power supply signals coming from the PC board to the first and the second power supply signal bond pads on the integrated circuit die.

Abstract: A test assembly for testing integrated circuits. The assembly includes a test chip that is located between the integrated circuit (IC) and a tester. The test chip has a very low input capacitance that approximates an open circuit, and has an impedance that matches the impedance of the integrated circuit and tester. The matching impedance of the test chip reduces the amount of signal ringing between the integrated circuit and tester.