Patents by Inventor Anna Su

Anna Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180029840
    Abstract: The present invention provides a handrail entry monitoring system of a passenger conveyor and a monitoring method thereof, and belongs to the field of passenger conveyor technologies. In the handrail entry monitoring system and the monitoring method of the present invention, at least part of a handrail entry region of the passenger conveyor is sensed by using an imaging sensor and/or a depth sensing sensor, to acquire a data frame, and the data frame is analyzed to monitor whether a handrail entry of the operating passenger conveyor is in a normal state or an abnormal state. The monitoring system of the present invention and the monitoring method thereof can timely and effectively detect a danger that a foreign matter is about to be entrapped into the handrail entry, helping prevent foreign matters from being entrapped into the handrail entry, thereby improving safety of the passenger conveyor.
    Type: Application
    Filed: July 28, 2017
    Publication date: February 1, 2018
    Inventors: LongWen Wang, ZhaoXia Hu, Hui Fang, Zhen Jia, Jianwei Zhao, Qiang Li, Anna Su, Alan Matthew Finn, Gero Gschwendtner
  • Publication number: 20160060079
    Abstract: The present invention relates to a rapid fixation means for a passenger conveyor. More specifically speaking, the present invention relates to a rapid fixation means for mounting into a fixed channel in a base of a lateral structure of a passenger conveyor, the rapid fixation means comprising a connector (4) and a buckle (5) assembly in coordination with one another, the connector (4) having supports capable of elastic deformation, the buckle (5) having a feature of forming a coordination with the supports of the connector (4), the coordination enabling the connector (4) and the buckle (5) to be rapidly joined and detached.
    Type: Application
    Filed: April 16, 2014
    Publication date: March 3, 2016
    Inventors: Adam Lu, Anna Su, MingLiang Yao, ZhengDong Gui, Benoit Dupont
  • Patent number: 5674354
    Abstract: A method for etching a conducting layer in a semiconductor device fabrication procedure is disclosed. The method provides for the formation of the conductor path with defined and precise control over the path width. The fabricated semiconductor device has a step-raised layer-covering structural configuration on a substrate, and the step-raised layer-covering structural configuration forms re-entrances when an insulation layer is formed over the step-raised layer-covering structure and the portion of the substrate surrounding the structure. The method includes forming a conducting layer on the insulation layer and then forming a shielding mask on the conducting layer for defining a conducting path with a predetermined pattern. The method further includes applying an anisotropic etching process for removing portions of the conducting layer not covered by the shielding mask. The method also forms residual stringers of the conducting layer in the re-entrances.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: October 7, 1997
    Assignee: United Microelectronics Corporation
    Inventors: Anna Su, Water Lur
  • Patent number: 5465003
    Abstract: A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: November 7, 1995
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, Anna Su, Neng H. Shen
  • Patent number: 5374583
    Abstract: A new method of local oxidation by means of forming a plurality of silicon trenches is described. Portions of the insulating layer over the surface of a silicon substrate not covered by a mask pattern are etched through exposing the portion of the silicon substrate that will form the device isolation region. A first trench is etched into the exposed portion of the substrate. A layer of silicon nitride is deposited over the insulating layer and within the trench. A layer of an aluminum-silicon alloy is deposited overlying the silicon nitride layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the silicon nitride layer. The nodules are oxidized to form silicon dioxide nodules. Using the silicon dioxide nodules as a mask, the silicon nitride layer is etched through to the insulating layer where it exists and to the silicon substrate surface where it is exposed and a set of narrow trenches is etched into the exposed portions of the substrate.
    Type: Grant
    Filed: May 24, 1994
    Date of Patent: December 20, 1994
    Assignee: United Microelectronic Corporation
    Inventors: Water Lur, Jiun Y. Wu, Anna Su
  • Patent number: 5372968
    Abstract: A method of local oxidation using trench-around technology is described. A first silicon oxide layer is deposited over the surface of a silicon substrate. A plurality of wide and narrow openings are etched through portions of the first silicon oxide layer not covered by a mask pattern to the silicon substrate. A layer of silicon nitride is patterned to form a set of spacers on the sidewalls of the patterned first silicon oxide layer which will fill the narrow openings. The first silicon oxide layer is partially etched away whereby the substrate within the central portions of the wide openings will be etched to form shallow trenches. The patterned first silicon oxide layer and the silicon nitride spacers are covered with spin-on-glass material which is baked and cured, then etched back leaving the spin-on-glass material only within the wide openings within the shallow trenches.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: December 13, 1994
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, Anna Su, Neng H. Shen
  • Patent number: 5308786
    Abstract: A first insulating layer is deposited over the surface of a silicon substrate. Those portions of the first insulating layers not covered by a mask pattern are etched through to the silicon substrate so as to provide a plurality of wide and narrow openings exposing portions of the silicon substrate that will form the device isolation regions. A second insulating layer is deposited overlying the patterned first insulating layer. A layer of an aluminum-silicon alloy is deposited overlying the second insulating layer. The aluminum-silicon layer is etched away whereby silicon nodules are formed on the surface of the second insulating layer. The second insulating layer is etched through to the first insulating layer where it exists and to the silicon substrate surface where the substrate is exposed within the wide and narrow openings. A first set of narrow trenches is etched into the exposed portions of the silicon substrate within the wide and narrow openings using the silicon nodules as a mask.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: May 3, 1994
    Assignee: United Microelectronics Corporation
    Inventors: Water Lur, Jiunn Y. Wu, Anna Su