Patents by Inventor Anna Tam
Anna Tam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9030155Abstract: Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.Type: GrantFiled: July 2, 2012Date of Patent: May 12, 2015Assignee: Pericom Semiconductor CorporationInventors: Xianxin Li, Hong-Leong Hong, Adbullah Raouf, Anna Tam, John Chi-Hung Hui, Tat C. Choi
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Patent number: 8966128Abstract: Apparatus and method generally relating to load detection associated with an analog video port are disclosed. An embodiment of the apparatus for detection of a remote termination resistance includes a pulse detection circuit configured to generate a detection pulse within a blanking interval. A pulse insertion circuit is coupled to receive the detection pulse and is configured to insert the detection pulse onto a line, where the line is an analog color signal line.Type: GrantFiled: December 13, 2012Date of Patent: February 24, 2015Assignee: Pericom SemiconductorInventors: Xianxin Li, Abdullah Raouf, Hong-Leong Hong, Anna Tam
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Patent number: 8237414Abstract: Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.Type: GrantFiled: April 15, 2009Date of Patent: August 7, 2012Assignee: Pericom Semiconductor CorporationInventors: Xianxin Li, Hong-Leong Hong, Adbullah Raouf, Anna Tam, John Chi-Hung Hui, Tat C. Choi
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Patent number: 8206115Abstract: An engine stage includes a row of airfoils joined to corresponding platforms to define flow passages therebetween. Each airfoil includes opposite pressure and suction sides and extends in chord between opposite leading and trailing edges. Extending from a surface of the platforms is a trailing edge ridge structure which adjoins the pressure sides, suction sides, and trailing edges of the airfoils with their respective platforms.Type: GrantFiled: September 26, 2008Date of Patent: June 26, 2012Assignee: General Electric CompanyInventors: Anurag Gupta, Brian Chandler Barr, Kevin Richard Kirtley, Anna Tam
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Publication number: 20100080708Abstract: An engine stage includes a row of airfoils joined to corresponding platforms to define flow passages therebetween. Each airfoil includes opposite pressure and suction sides and extends in chord between opposite leading and trailing edges. Extending from a surface of the platforms is a trailing edge ridge structure which adjoins the pressure sides, suction sides, and trailing edges of the airfoils with their respective platforms.Type: ApplicationFiled: September 26, 2008Publication date: April 1, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Anurag Gupta, Brian Chandler Barr, Kevin Richard Kirtkey, Anna Tam
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Patent number: 7545834Abstract: A switch fabric that carries analog differential signals is constructed from 2×2 switches. Each 2×2 switch has two differential inputs that are applied to two demultiplexers. Each 2×2 switch also has two differential outputs, each driven by an equalizing mux. Each demultiplexer has two amplifiers that drive intermediate differential signals to the two equalizing muxes. Each equalizing mux has two equalizers that receive the intermediate differential signals from the two demultiplexers. A select signal enables one equalizer but disables the other to select one of the two intermediate differential inputs. A combining amplifier receives differential outputs from both equalizers and generates a final differential output. R, C values in each equalizer can be adjusted to compensate for loading variations in the intermediate differential signals which can have different physical lengths in a switch fabric.Type: GrantFiled: January 10, 2006Date of Patent: June 9, 2009Assignee: Pericom Semiconductor Corp.Inventors: Zhangqi Guo, Anna Tam
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Patent number: 7220100Abstract: A turbine stage includes a row of airfoils joined to corresponding platforms to define flow passages therebetween. Each airfoil includes opposite pressure and suction sides and extends in chord between opposite leading and trailing edges. Each platform includes a crescentic ramp increasing in height from the leading and trailing edges toward the midchord of the airfoil along the pressure side thereof.Type: GrantFiled: April 14, 2005Date of Patent: May 22, 2007Assignee: General Electric CompanyInventors: Ching-Pang Lee, Anna Tam, Kevin Richard Kirtley, Scott Henry Lamson
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Patent number: 7134842Abstract: A turbine stage includes a row of airfoils joined to corresponding platforms to define flow passages therebetween. Each airfoil includes opposite pressure and suction sides and extends in chord between opposite leading and trailing edges. Each platform has a scalloped flow surface including a bulge adjoining the pressure side adjacent the leading edge, and a bowl adjoining the suction side aft of the leading edge.Type: GrantFiled: December 24, 2004Date of Patent: November 14, 2006Assignee: General Electric CompanyInventors: Anna Tam, Ching-Pang Lee, Kevin Richard Kirtley, Ronald Scott Bunker, Scott Henry Lamson, Scott Michael Carson
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Publication number: 20060233641Abstract: A turbine stage includes a row of airfoils joined to corresponding platforms to define flow passages therebetween. Each airfoil includes opposite pressure and suction sides and extends in chord between opposite leading and trailing edges. Each platform includes a crescentic ramp increasing in height from the leading and trailing edges toward the midchord of the airfoil along the pressure side thereof.Type: ApplicationFiled: April 14, 2005Publication date: October 19, 2006Inventors: Ching-Pang Lee, Anna Tam, Kevin Kirtley, Scott Lamson
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Publication number: 20060140768Abstract: A turbine stage includes a row of airfoils joined to corresponding platforms to define flow passages therebetween. Each airfoil includes opposite pressure and suction sides and extends in chord between opposite leading and trailing edges. Each platform has a scalloped flow surface including a bulge adjoining the pressure side adjacent the leading edge, and a bowl adjoining the suction side aft of the leading edge.Type: ApplicationFiled: December 24, 2004Publication date: June 29, 2006Inventors: Anna Tam, Ching-Pang Lee, Kevin Kirtley, Ronald Bunker, Scott Lamson, Scott Carson
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Patent number: 6724592Abstract: Pin-to-pin electro-static-discharge (ESD) protection is provided for a bus-switch transistor that is connected to I/O pins at its source and drain. A p-type substrate is normally pumped below ground by a substrate bias generator when power is applied. However, during a pin-to-pin ESD test, power and ground are floating. A gate node is pulled high through a coupling capacitor by the ESD pulse. The gate node turns on a shunting transistor to couple the ESD pulse to the floating ground bus. The gate node also turns on a shorting transistor that connects the floating ground bus to the floating substrate. A resistor drains the coupling capacitor to the substrate, rather than to ground. Current is injected into the substrate by the resistor. The snapback voltage is lowered by substrate-triggering.Type: GrantFiled: December 11, 2002Date of Patent: April 20, 2004Assignee: Pericom Semiconductor Corp.Inventors: Paul C. F. Tong, Ming-Dou Ker, Ping Ping Xu, Kwong Shing Lin, Anna Tam
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Patent number: 6081004Abstract: A repeating cell structure in a semiconductor substrate for a BiCMOS logic gate array. The cell structure has three regions shaped as columns. The first columnar region is a P-well and has four vertically aligned active areas of N-type material formed within the columnar region. Each of the active areas has two gate electrodes to form two NMOS transistors. Similarly the second columnar region is a N-well and has four vertically aligned active areas of P-type material. Each such active region forms two PMOS transistors. The third column has two bipolar transistors, each with collector, base and emitter regions vertically aligned. The resulting BiCMOS logic array permits a flexible location of macrocells, which results in a compact implementation of the resulting integrated circuit.Type: GrantFiled: March 27, 1995Date of Patent: June 27, 2000Assignee: LSI Logic Corp.Inventors: Anthony Y. Wong, Anna Tam, Daniel Wong