Patents by Inventor Anna Topol
Anna Topol has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090014878Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric.Type: ApplicationFiled: May 30, 2008Publication date: January 15, 2009Applicant: International Business Machines CorporationInventors: Cyril Cabral, JR., Hariklia Deligianni, Randolph F. Knarr, Sandra G. Malhotra, Stephen Rossnagel, Xiaoyan Shao, Anna Topol, Philippe M. Vereecken
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Publication number: 20080277778Abstract: A structure for a semiconductor components is provided having a device layer sandwiched on both sides by other active, passive, and interconnecting components. A wafer-level layer transfer process is used to create this planar (2D) IC structure with added functional enhancements.Type: ApplicationFiled: May 10, 2007Publication date: November 13, 2008Inventors: Bruce K. Furman, Sampath Purushothaman, Muthumanickam Sankarapandian, Anna Topol
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Patent number: 7405154Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric.Type: GrantFiled: March 24, 2006Date of Patent: July 29, 2008Assignee: International Business Machines CorporationInventors: Cyril Cabral, Jr., Hariklia Deligianni, Randolph F. Knarr, Sandra G. Malhotra, Stephen Rossnagel, Xiaoyan Shao, Anna Topol, Philippe M. Vereecken
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Publication number: 20080164494Abstract: Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Francois Pagette, Christian Lavoie, Anna Topol
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Publication number: 20080157404Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.Type: ApplicationFiled: January 2, 2007Publication date: July 3, 2008Inventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Publication number: 20080157260Abstract: A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.Type: ApplicationFiled: January 2, 2007Publication date: July 3, 2008Inventors: David Michael Fried, John Michael Hergenrother, Sharee Jane McNab, Michael J. Rooks, Anna Topol
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Patent number: 7394113Abstract: Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer.Type: GrantFiled: July 26, 2006Date of Patent: July 1, 2008Assignee: International Business Machines CorporationInventors: Francois Pagette, Anna Topol
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Publication number: 20080121936Abstract: Embodiments herein present a structure, method, etc. for a self-alignment scheme for a heterojunction bipolar transistor (HBT). An HBT is provided, comprising an extrinsic base, a first self-aligned silicide layer over the extrinsic base, and a nitride etch stop layer above the first self-aligned silicide layer. A continuous layer is also included between the first self-aligned silicide layer and the nitride etch stop layer, wherein the continuous layer can comprise oxide. The HBT further includes spacers adjacent the continuous layer, wherein the spacers and the continuous layer separate the extrinsic base from an emitter contact. In addition, an emitter is provided, wherein the height of the emitter is less than or equal to the height of the extrinsic base. Moreover, a second self-aligned silicide layer is over the emitter, wherein the height of the second silicide layer is less than or equal to the height of the first silicide layer.Type: ApplicationFiled: July 26, 2006Publication date: May 29, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Francois Pagette, Anna Topol
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Publication number: 20080042291Abstract: Contact via structures using a hybrid barrier layer, are disclosed. One contact via structure includes: an opening through a dielectric to a silicide region; a first layer in the opening in direct contact with the silicide region, wherein the first layer is selected from the group consisting of: titanium (Ti) and tungsten nitride (WN); at least one second layer over the first layer, the at least one second layer selected from the group consisting of: tantalum nitride (TaN), titanium nitride (TiN), tantalum (Ta), ruthenium (Ru), rhodium (Rh), platinum (Pt) and cobalt (Co); a seed layer for copper (Cu); and copper (Cu) filling a remaining portion of the opening.Type: ApplicationFiled: August 21, 2006Publication date: February 21, 2008Inventors: Randolph F. Knarr, Christopher D. Sheraw, Andrew H. Simon, Anna Topol, Yun-Yu Wang, Keith Kwong Hon Wong
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Publication number: 20070284654Abstract: A transistor device and method are disclosed for reducing parasitic resistance and enhancing channel mobility using a metal alloy layer over a conductive region. A transistor device may include a conductive region such as a source, drain and/or gate including at least one first conductive material, and a metal alloy layer disposed on substantially all of a surface of the conductive region, the metal alloy layer including a second conductive material different than the at least one first conductive materials. In one embodiment, the second conductive material includes a cobalt and/or nickel alloy. The metal alloy layer provides a non-epitaxial raised source/drain (and gate) to reduce the parasitic series resistance in, for example, nFETs fabricated on UTSOI. In addition, the metal alloy layer may include a stress to enhance mobility in a channel of the transistor device. The metal alloy layer may be formed using a selective electrochemical metal deposition process such as electroless or electrolytic plating.Type: ApplicationFiled: June 8, 2006Publication date: December 13, 2007Inventors: Judith M. Rubino, James Pan, Dinkar Singh, Jonathan Smith, Anna Topol
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Publication number: 20070281439Abstract: Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a thee dimensional integrated structure is provided.Type: ApplicationFiled: August 17, 2007Publication date: December 6, 2007Inventors: Stephen Bedell, Keith Fogel, Bruce Furman, Sampath Purushothaman, Devendra Sadana, Anna Topol
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Publication number: 20070222066Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric.Type: ApplicationFiled: March 24, 2006Publication date: September 27, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Cyril Cabral, Hariklia Deligianni, Randolph Knarr, Sandra Malhotra, Stephen Rossnagel, Xiaoyan Shao, Anna Topol, Philippe Vereecken
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Publication number: 20070218641Abstract: A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.Type: ApplicationFiled: March 14, 2006Publication date: September 20, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Ahlgren, Guy Cohen, Christian Lavoie, Francois Pagette, Anna Topol
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Publication number: 20070145533Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.Type: ApplicationFiled: February 22, 2007Publication date: June 28, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David AHLGREN, Gregory FREEMAN, Francois PAGETTE, Christopher SCHNABEL, Anna TOPOL
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Publication number: 20050269664Abstract: A bipolar transistor has a collector that is contacted directly beneath a base-collector junction by metallization to reduce collector resistance. A conventional reach-through and buried layer, as well as their associated resistance, are eliminated. The transistor is well isolated, nearly eliminating well-to-substrate capacitance and device-to-device leakage current. The structure provides for improved electrical performance, including improved fT, Fmax and drive current.Type: ApplicationFiled: June 4, 2004Publication date: December 8, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Ahlgren, Gregory Freeman, Francois Pagette, Christopher Schnabel, Anna Topol
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Publication number: 20050082526Abstract: Techniques for the fabrication of semiconductor devices are provided. In one aspect, a layer transfer structure is provided. The layer transfer structure comprises a carrier substrate having a porous region with a tuned porosity in combination with an implanted species defining a separation plane therein. In another aspect, a method of forming a layer transfer structure is provided. In yet another aspect, a method of forming a three dimensional integrated structure is provided.Type: ApplicationFiled: October 15, 2003Publication date: April 21, 2005Applicant: International Business Machines CorporationInventors: Stephen Bedell, Keith Fogel, Bruce Furman, Sampath Purushothaman, Devendra Sadana, Anna Topol