Abstract: In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value.

Abstract: In an apparatus relating generally to an IC die, the IC die has a regulated power supply, a power supply grid, and a test circuit. The regulated power supply is biased between a source supply node and a source ground node, which are externally accessible nodes of the IC die. An internal supply node of the power supply grid is coupled to the regulated power supply. The test circuit is coupled to the internal supply node of the power supply grid. The test circuit is configured to test for at least one short in the power supply grid. The test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance. The test circuit is configured to test for the at least one short in presence of background current leakage of the power supply grid.