Patents by Inventor Anna Zhang
Anna Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194531Abstract: A 3D integrated structure and a method for fabricating the structure. In the method, a first trimming process is performed in a peripheral region of a wafer stack to form a chamfered surface adjacent to and surrounding an active device region. As a result, a thickness of the wafer stack along the chamfered surface gradually decreases from an edge of the active device region outward. In this way, a photoresist layer can be subsequently easily applied to cover the junction of the active device region and the chamfered surface, without the formation of discontinuities there, which may affect the subsequent processes. Additionally, in the method, a second trimming process is performed at an edge of the peripheral region to form a clamping surface adjacent to and surrounding the chamfered surface. In this way, it is unnecessary to clamp the wafer stack at a top surface thereof.Type: ApplicationFiled: December 7, 2022Publication date: June 13, 2024Inventors: Anna ZHANG, Yu ZHOU, Sheng HU
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Publication number: 20190054060Abstract: Therapy for influenza using a combination of a neuraminidase inhibitor, a macrolide antibiotic, and a non-steroidal anti-inflammatory drug has been found to provide improved clinical outcomes and reduced incidence of viral quasispecies compared to conventional treatment with neuraminidase inhibitors alone. Effective treatment schedules are also provided. The drug combination can be used in concert with a proton-pump inhibitor and/or an additional antibacterial antibiotic.Type: ApplicationFiled: March 1, 2016Publication date: February 21, 2019Inventors: Ivan Fan Ngai HUNG, Kai Wang Kelvin TO, Jinxia Anna ZHANG, Fuk Woo Jasper CHAN, Manson FOK, Johnson Yiu-Nam LAU, Kwok-Yung YUEN
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Patent number: 9728472Abstract: A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.Type: GrantFiled: December 31, 2013Date of Patent: August 8, 2017Assignee: CSMC Technologies FAB1 Co., Ltd.Inventors: Anna Zhang, Xiaoming Li
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Patent number: 9431308Abstract: A critical dimension compensating method of a deep trench etching process includes: obtaining an etching critical dimension difference; compensating an masking layer layout for wafer etching according to a distance between an etching position and the center position of the wafer, and the etching critical dimension difference; and performing a deep trench etching to the wafer according to the compensated masking layer layout. The dimension of the etching patterns of the masking layer layout is compensated by using half of the critical dimension difference as the compensation value, such that the etch rate difference and the etching dimension difference caused by uneven distribution of the critical dimension at different wafer locations during the deep trench etching process are improved, thus greatly improving the uniformity of the critical dimension of the deep trench etching structure.Type: GrantFiled: December 31, 2013Date of Patent: August 30, 2016Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.Inventors: Anna Zhang, Xiaoming Li
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Publication number: 20150332981Abstract: A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.Type: ApplicationFiled: December 31, 2013Publication date: November 19, 2015Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.Inventors: Anna ZHANG, Xiaoming LI
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Publication number: 20150279749Abstract: A critical dimension compensating method of a deep trench etching process includes: obtaining an etching critical dimension difference; compensating an masking layer layout for wafer etching according to a distance between an etching position and the center position of the wafer, and the etching critical dimension difference; and performing a deep trench etching to the wafer according to the compensated masking layer layout. The dimension of the etching patterns of the masking layer layout is compensated by using half of the critical dimension difference as the compensation value, such that the etch rate difference and the etching dimension difference caused by uneven distribution of the critical dimension at different wafer locations during the deep trench etching process are improved, thus greatly improving the uniformity of the critical dimension of the deep trench etching structure.Type: ApplicationFiled: December 31, 2013Publication date: October 1, 2015Inventors: Anna Zhang, Xiaoming Li
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Patent number: 8135713Abstract: An intelligent sourcing controller for sourcing potential suppliers from external sources such as the Internet as well as internal sources such as a local data server. The intelligent sourcing engine controller provides a supplier appraisal to the buyer as decision support. The intelligent sourcing controller integrates its supplier appraisal criteria with the buyer's sourcing criteria, classifying the collected information in the same way a buyer configures his requirements for the suppliers. The intelligent sourcing controller synchronizes the Internet sourcing results with the local data server after each search to renew data in the local data server in time and the sourcing criteria can be reused in future for decision support.Type: GrantFiled: March 31, 2006Date of Patent: March 13, 2012Assignee: SAP AGInventors: Simon Chen, Fred Chen, Anna Zhang, Tian Xu, Jay Xiong
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Publication number: 20070250330Abstract: An intelligent sourcing controller for sourcing potential suppliers from external sources such as the Internet as well as internal sources such as a local data server. The intelligent sourcing engine controller provides a supplier appraisal to the buyer as decision support. The intelligent sourcing controller integrates its supplier appraisal criteria with the buyer's sourcing criteria, classifying the collected information in the same way a buyer configures his requirements for the suppliers. The intelligent sourcing controller synchronizes the Internet sourcing results with the local data server after each search to renew data in the local data server in time and the sourcing criteria can be reused in future for decision support.Type: ApplicationFiled: March 31, 2006Publication date: October 25, 2007Applicant: SAP AGInventors: Simon Chen, Fred Chen, Anna Zhang, Tian Xu, Jay Xiong