Patents by Inventor Annalisa Cappelani

Annalisa Cappelani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors
    Patent number: 6800898
    Abstract: The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.
    Type: Grant
    Filed: September 12, 2001
    Date of Patent: October 5, 2004
    Assignee: Infineon Technologies AG
    Inventors: Annalisa Cappelani, Bernhard Sell, Josef Willer
  • Integrated circuit configuration and method of fabricating a dram structure with buried bit lines or trench capacitors
    Publication number: 20030034512
    Abstract: The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.
    Type: Application
    Filed: September 12, 2001
    Publication date: February 20, 2003
    Inventors: Annalisa Cappelani, Bernhard Sell, Josef Willer