Patents by Inventor Annalisa Cappellani

Annalisa Cappellani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10424580
    Abstract: Semiconductor devices having modulated nanowire counts and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a plurality of nanowires disposed above a substrate and stacked in a first vertical plane with a first uppermost nanowire. A second semiconductor device has one or more nanowires disposed above the substrate and stacked in a second vertical plane with a second uppermost nanowire. The second semiconductor device includes one or more fewer nanowires than the first semiconductor device. The first and second uppermost nanowires are disposed in a same plane orthogonal to the first and second vertical planes.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Gopinath Bhimarasetti, Tahir Ghani, Seiyon Kim
  • Publication number: 20190157411
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Application
    Filed: January 22, 2019
    Publication date: May 23, 2019
    Inventors: Annalisa CAPPELLANI, Abhijit Jayant PETHE, Tahir GHANI, Harry GOMEZ
  • Publication number: 20190115257
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Application
    Filed: December 13, 2018
    Publication date: April 18, 2019
    Inventors: Abhijit Jayant PETHE, Tahir GHANI, Mark BOHR, Clair WEBB, Harry GOMEZ, Annalisa CAPPELLANI
  • Patent number: 10229981
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 10192783
    Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Abhijit Jayant Pethe, Tahir Ghani, Mark Bohr, Clair Webb, Harry Gomez, Annalisa Cappellani
  • Patent number: 10074573
    Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: September 11, 2018
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea, Rafael Rios, Glenn A. Glass
  • Patent number: 10026829
    Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
    Type: Grant
    Filed: February 16, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Stephen M. Cea, Tahir Ghani, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys, Seiyon Kim, Kelin J. Kuhn, Aaron D. Lilak, Rafael Rios, Mayank Sahni
  • Patent number: 9978636
    Abstract: Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Kelin J. Kuhn, Rafael Rios, Harry Gomez
  • Patent number: 9905650
    Abstract: Uniaxially strained nanowire structures are described. For example, a semiconductor device includes a plurality of vertically stacked uniaxially strained nanowires disposed above a substrate. Each of the uniaxially strained nanowires includes a discrete channel region disposed in the uniaxially strained nanowire. The discrete channel region has a current flow direction along the direction of the uniaxial strain. Source and drain regions are disposed in the nanowire, on either side of the discrete channel region. A gate electrode stack completely surrounds the discrete channel regions.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: February 27, 2018
    Assignee: Intel Corporation
    Inventors: Stephen M. Cea, Seiyon Kim, Annalisa Cappellani
  • Patent number: 9691843
    Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Glenn A. Glass, Van H. Le
  • Publication number: 20170162676
    Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Annalisa CAPPELLANI, Stephen M. CEA, Tahir GHANI, Harry GOMEZ, Jack T. KAVALIEROS, Patrick H. KEYS, Seiyon KIM, Kelin J. KUHN, Aaron D. LILAK, Rafael RIOS, Mayank SAHNI
  • Patent number: 9673302
    Abstract: Techniques are disclosed for converting a strain-inducing semiconductor buffer layer into an electrical insulator at one or more locations of the buffer layer, thereby allowing an above device layer to have a number of benefits, which in some embodiments include those that arise from being grown on a strain-inducing buffer and having a buried electrical insulator layer. For instance, having a buried electrical insulator layer (initially used as a strain-inducing buffer during fabrication of the above active device layer) between the Fin and substrate of a non-planar integrated transistor circuit may simultaneously enable a low-doped Fin with high mobility, desirable device electrostatics and elimination or otherwise reduction of substrate junction leakage. Also, the presence of such an electrical insulator under the source and drain regions may further significantly reduce junction leakage. In some embodiments, substantially the entire buffer layer is converted to an electrical insulator.
    Type: Grant
    Filed: October 17, 2016
    Date of Patent: June 6, 2017
    Assignee: INTEL CORPORATION
    Inventors: Annalisa Cappellani, Van H. Le, Glenn A. Glass, Kelin J. Kuhn, Stephen M. Cea
  • Publication number: 20170141239
    Abstract: Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.
    Type: Application
    Filed: January 13, 2017
    Publication date: May 18, 2017
    Inventors: Stephen M. CEA, Annalisa CAPPELLANI, Martin D. GILES, Rafael RIOS, Seiyon KIM, Kelin J. KUHN
  • Publication number: 20170133277
    Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Inventors: Seiyon KIM, Kelin J. KUHN, Tahir GHANI, Anand S. MURTHY, Annalisa CAPPELLANI, Stephen M. CEA, Rafael RIOS, Glenn A. GLASS
  • Publication number: 20170133462
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Application
    Filed: January 19, 2017
    Publication date: May 11, 2017
    Inventors: Kelin J. KUHN, Seiyon KIM, Rafael RIOS, Stephen M. CEA, Martin D. GILES, Annalisa CAPPELLANI, Titash RAKSHIT, Peter CHANG, Willy RACHMADY
  • Publication number: 20170125591
    Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
    Type: Application
    Filed: January 17, 2017
    Publication date: May 4, 2017
    Inventors: Martin D. GILES, Annalisa CAPPELLANI, Sanaz KABEHIE, Rafael RIOS, Cory E. WEBER, Aaron A. BUDREVICH
  • Patent number: 9608059
    Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Stephen M. Cea, Tahir Ghani, Harry Gomez, Jack T. Kavalieros, Patrick H. Keys, Seiyon Kim, Kelin J. Kuhn, Aaron D. Lilak, Rafael Rios, Mayank Sahni
  • Patent number: 9595581
    Abstract: Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Kelin J. Kuhn, Seiyon Kim, Rafael Rios, Stephen M. Cea, Martin D. Giles, Annalisa Cappellani, Titash Rakshit, Peter Chang, Willy Rachmady
  • Patent number: 9583491
    Abstract: Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Seiyon Kim, Kelin J. Kuhn, Tahir Ghani, Anand S. Murthy, Annalisa Cappellani, Stephen M. Cea, Rafael Rios, Glenn A. Glass
  • Patent number: 9583487
    Abstract: Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above a semiconducting channel region of a substrate. Metallic source and drain regions are disposed above the substrate, on either side of the semiconducting channel region. Each of the metallic source and drain regions has a profile. A first semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic source region, and conformal with the profile of the metallic source region. A second semiconducting out-diffusion region is disposed in the substrate, between the semiconducting channel region and the metallic drain region, and conformal with the profile of the metallic drain region.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 28, 2017
    Assignee: Intel Corporation
    Inventors: Martin D. Giles, Annalisa Cappellani, Sanaz Kabehie, Rafael Rios, Cory E. Weber, Aaron A. Budrevich