Abstract: The invention relates to a circuit architecture for processing multi-channel frames of broadband synchronous digital signals, in particular signals of the SONET/SDH standard. The circuit includes an input portion and an output portion. It also contains at least one modular component adapted to process frames comprising a single channel and connectable modularly to N further identical components corresponding to the number of frame channels.

Abstract: The process of synchronization and decomposition of asynchronous frames organized with octet-rows of bits, for the adaptation of speed carried out by an intermediate reception block for adaptation of speed of an integrated device for the adaptation of synchronous and asynchronous terminals according to the CCITT V.110 standard to an Integrated Service Digital Network, is carried out by storing one octet at a time in an 8-bit shift register and by using counters in order to store the current position of each octet within a respective asynchronous frame and by recognizing by means of other counters and relevant bits of each octet, which are stored and switched to the respective elements for management and for control of the serial flow of data from the network to the terminal. From this, an architecture is derived, which is particularly simplified by means of the redimensioning of the registers which, instead of storing an entire frame, have to store only one octet at a time.