Patents by Inventor Anne AUGUSTINE
Anne AUGUSTINE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063183Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.Type: ApplicationFiled: August 19, 2022Publication date: February 22, 2024Applicant: Intel CorporationInventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Anne Augustine, Beomseok Choi, Kimin Jun, Omkar G. Karhade, Shawna M. Liff, Julien Sebot, Johanna M. Swan, Krishna Vasanth Valavala
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Publication number: 20230319997Abstract: Embodiments herein relate to systems, apparatuses, or processes to using vias, or plated through holes (PTH), within a substrate or within a sub laminate to create capacitors. The interior of a via may have a first layer, or coating, of an electrically conductive material such as copper, formed on the sides of the via. A second layer including a dielectric material is placed on the first layer of the electrically conductive material. A third layer of electrically conductive material may then be placed on the second layer of the dielectric material. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Aslam HASWAREY, Anne AUGUSTINE, Yan Fen SHEN
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Patent number: 11690165Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.Type: GrantFiled: April 13, 2022Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Michael J. Hill, Huong T. Do, Anne Augustine
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Publication number: 20220293327Abstract: An inductor can be formed in a coreless electronic substrate, such that the fabrication process does not result in the magnetic material used in the inductor leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming conductive vias with a lithographic process, rather than a standard laser process, in combination with panel planarization to prevent exposure of the magnetic material to the plating and/or etching solutions/chemistries.Type: ApplicationFiled: March 11, 2021Publication date: September 15, 2022Applicant: Intel CorporationInventors: Sanka Ganesan, Sri Chaitra Jyotsna Chavali, Robert L. Sankman, Anne Augustine, Kaladhar Radhakrishnan
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Publication number: 20220240370Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.Type: ApplicationFiled: April 13, 2022Publication date: July 28, 2022Applicant: Intel CorporationInventors: Michael J. Hill, Huong T. Do, Anne Augustine
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Patent number: 11357096Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.Type: GrantFiled: July 5, 2018Date of Patent: June 7, 2022Assignee: Intel CorporationInventors: Michael J. Hill, Huong T. Do, Anne Augustine
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Patent number: 11335620Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.Type: GrantFiled: July 13, 2018Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Michael J. Hill, Anne Augustine, Huong Do, William Lambert
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Publication number: 20220093536Abstract: Embodiments disclosed herein include coreless interposers with embedded inductors. In an embodiment, a coreless interposer comprises a plurality of buildup layers, where electrical routing is provided in the plurality of buildup layers. In an embodiment, the coreless interposer further comprises an inductor embedded in the plurality of buildup layers. In an embodiment, the inductor comprises a magnetic shell, and a conductive lining over an interior surface of the magnetic shell.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Inventors: Krishna BHARATH, William J. LAMBERT, Haifa HARIRI, Siddharth KULASEKARAN, Mathew MANUSHAROW, Anne AUGUSTINE
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Publication number: 20200020652Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.Type: ApplicationFiled: July 13, 2018Publication date: January 16, 2020Applicant: Intel CorporationInventors: Michael J. Hill, Anne Augustine, Huong Do, William Lambert
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Publication number: 20200015348Abstract: Embodiments include a microelectronic device package structure having an inductor within a portion of a substrate, wherein a surface of the inductor is substantially coplanar with a surface of the substrate. One or more thermal interconnect structures are on the surface of the inductor. A conductive feature is embedded within a board, where a surface of the conductive feature is substantially coplanar with a surface of the board. One or more thermal interconnect structures are on the surface of the conductive feature of the board, where the thermal interconnect structures provide a thermal pathway for cooling for the inductor.Type: ApplicationFiled: July 5, 2018Publication date: January 9, 2020Applicant: Intel CorporationInventors: Michael J. Hill, Huong T. Do, Anne Augustine
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Publication number: 20200013533Abstract: A microelectronics package, comprising a substrate that comprises a dielectric and an inductor component comprising one or more wires within a magnetic core over the dielectric. The inductor component is bonded to the substrate by one or more solder joints. A solder mask is between the inductor component and the dielectric. The one or more solder joints are surrounded by the solder mask, and wherein the solder mask comprises a magnetic material.Type: ApplicationFiled: July 3, 2018Publication date: January 9, 2020Applicant: Intel CorporationInventors: Malavarayan SANKARASUBRAMANIAN, Anne AUGUSTINE, Yongki MIN, Kaladhar RADHAKRISHNAN
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Publication number: 20200005983Abstract: Embodiments herein relate to a magnetic encapsulant composite, comprising a mixture of a first material that is a soft magnetic filler, a second material that is a polymer matrix, and a third material that is a process ingredient. The magnetic encapsulant composite may then encapsulate or partially encapsulate a magnetic inductor coupled to a substrate to increase the inductance of the magnetic inductor and/or to strengthen the substrate to which the magnetic inductor and the composite are coupled.Type: ApplicationFiled: June 29, 2018Publication date: January 2, 2020Inventors: Malavarayan SANKARASUBRAMANIAN, Yongki MIN, Anne AUGUSTINE, Kaladhar RADHAKRISHNAN, Taylor GAINES, Ziyin LIN