Abstract: This disclosure relates to semiconductor varactors, such as thin film poly-Si varactors, which have larger effective gate areas in accumulation than in depletion, together with capacitive switching ratios which are essentially determined by the ratio of their effective gate area in accumulation to their effective gate area in depletion. To that end, such a varactor has a fully depletable active semiconductor layer, such as a thin poly-Si film, and is constructed so that at least a part of its active layer is sandwiched between a relatively thin dielectric layer and a relatively thick dielectric layer. The thin dielectric layer, in turn, is sandwiched between the active semiconductor layer and a gate electrode. Furthermore, one or more ground electrodes are electrically coupled to laterally offset portions of the active semiconductor layer in partial overlapping alignment with the gate electrode.

Abstract: A thin film SOI CMOS device wherein the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

Abstract: A thin film SOI CMOS device wheren the suitably doped deposited layers of an n-channel transistor and a p-channel transistor are simultaneously deposited. The source and drain elements of one transistor and the gate element of the other transistor are formed in a lower, highly doped, semiconductor layer and are separated from the corresponding gate element and source and drain elements formed in an upper, highly doped, semiconductor layer. The layer levels are separated by two intrinsic or lightly doped semiconductor layers sandwiching a dielectric layer, so that the intrinsic or lightly doped semiconductor layer lying contiguous to the source and drain elements serves as an active channel layer and the intrinsic or lightly doped semiconductor layer lying contiguous to the gate element serves to extend the gate layer.

Abstract: A method of forming large grain polycrystalline films by deep ion implantation into a composite structure, comprising a layer of amorphous semiconductor material upon an insulating substrate. Implantation is of a given ion species at an implant energy and dosage sufficient to distrupt the interface between the amorphous layer and the substrate and to retard the process of nucleation in subsequent random crystallization upon thermal annealing.

Abstract: A depletion mode thin film semiconductor photodetector comprises a crystalline silicon thin film on an insulating substrate with a source region, a drain region and a thin film light sensing channel region formed therebetween. A gate oxide formed over the channel region and a gate electrode formed on the gate oxide. A p-n junction located parallel to the surface of the substrate and within the thin film functioning as a space charge separation region in the channel. The lower portion of the channel region is a p region extending to the substrate and the upper portion of the channel region is a n region extending to the gate oxide. The channel region functions as a fully depleted channel when the photodetector is operated in its OFF state providing for high dynamic range and large photocurrent operation. The depletion mode thin film semiconductor photodetector with n.sup.+ source and drain regions function as an ohmic contacts to the channel n region forming a thin film transistor.

Abstract: A method for eliminating laser induced substrate fissures associated with laser annealed crystallization of patterned silicon areas, for increasing the yield of useable single crystal areas. The fissures are created by enhanced etching of the substrate, at the exposed edges of the areas, during the removal of a dimension stabilizing encapsulating layer. A post crystallization, high temperature anneal, in an oxidizing atmosphere prevents the enhanced etching of the substrate.

Abstract: A suspension for electrophoretic display systems, such as the display systems shown in U.S. Pat. No. 3,668,106, is described. The particles in the suspension are coated with a highly fluorinated polymeric material, which acts as a dispersant. Preferably, the suspension also includes a charge control agent.

Abstract: Electrophoretic display device containing a suspension of hollow particles in an insulating medium, wherein the weight density of the particles is equal to, or within five percent of, that of the insulating medium. Settling out of the particles is, thus, greatly reduced or eliminated during periods of non-use.