Abstract: Described herein are embodiments of a slurry used for the chemical mechanical polishing a substrate that includes aluminum or an aluminum alloy features having a width of less than 1 um. The slurry includes a precipitated silica abrasive having a diameter of less than or equal to 100 nm and a chelating buffer system comprising citric acid and oxalic acid to provide a pH of the slurry in the approximate range of 1.5 and 4.0.

Abstract: Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising at least one opening, and then applying a nanotube slurry comprising at least one nanotube to the substrate, wherein the at least one nanotube is substantially placed within the at least one opening.

Abstract: Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal treatment process. Electropolishing is then used to planarize the second and first conductive films, wherein an electrolyte solution selective to remove the first conductive film faster than the second conductive film is used. An interconnect is formed.

Abstract: A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

Abstract: In one embodiment, the present invention includes a method for forming a dielectric layer on a semiconductor wafer and patterning at least one opening in the dielectric layer, depositing a barrier layer over the dielectric layer, depositing a conductive layer over the barrier layer, and electropolishing the conductive layer while ultrasonically agitating the semiconductor wafer until a predetermined amount of the conductive layer remains over the barrier layer. Other embodiments are described and claimed.

Abstract: A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.

Abstract: Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal treatment process. Electropolishing is then used to planarize the second and first conductive films, wherein an electrolyte solution selective to remove the first conductive film faster than the second conductive film is used. An interconnect is formed.

Abstract: Methods of fabricating an interconnect, which fundamentally comprises etching back on an overhang section formed over a portion of an opening formed in a dielectric layer, said etching back is selected from one of an electropolishing process and chemical etching process, and said etching back removes the overhang section at a controlled etch rate of about 10 ?/sec to 70 ?/sec; and depositing a conductive material into the opening so as to fill the opening and form an interconnect.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: Slurries and methods for the chemical mechanical polishing of high density copper interconnects in a low k ILD are presented. In a particular embodiment of the present invention, a slurry for polishing copper is formed by combining a surfactant comprising an alkyl ethoxy organic acid such as glycolic acid ethoxylate lauryl ether (GAELE), an abrasive such as silica, an oxidizing agent such as hydrogen peroxide, and a chelating buffer system such as citric acid and potassium citrate dissolved in the mixture. This slurry provides a very low incidence of bent line defects, a low erosion rate, and a low dishing rate on a substrate comprising high density copper interconnects in a low k ILD. Embodiments of methods of the present invention use the disclosed slurries.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.

Abstract: A method of forming a microelectronic structure and its associated structures is described. In one embodiment, a substrate is provided with a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrificial layer. The metal layer is then removed at a first removal rate wherein a dishing is induced on a top surface of the metal layer until the sacrificial layer is exposed, and simultaneously removing the metal layer and the sacrificial layer at a second removal rate without substantially removing the hard mask.

Abstract: A slurry for copper polishing has a pH between 7.5 and 12. In a particular embodiment of the present invention, a slurry for polishing copper has a pH between 8 and 11.5, and includes a siO2 abrasive, a (NH4)2S2O8 oxidizer, a benzotriazole corrosion inhibitor, and a K3PO4/K2HPO4 buffer. A copper polish slurry, in accordance with the present invention, operates with a high pH of greater than approximately 7.5. In this range the slurry has a low static etch due to formation of a robust, protective layer. This slurry may additionally have S2O8?2 or Fe(CN)6 ?3 as an oxidizer and can thus offer a high polish rate on the order of 7,000 to 10,000 angstroms per minute which does not decrease significantly during polishing. Such an inventive slurry offers a wide CMP process window such that the slurry and process parameters can be optimized to yield low recess, erosion, and dishing on patterned wafers.

Abstract: A method of forming a microelectronic structure and its associated structures is described. In one embodiment, a substrate is provided with a sacrificial layer disposed on a hard mask layer, and a metal layer disposed in a trench of the substrate and on the sacrificial layer. The metal layer is then removed at a first removal rate wherein a dishing is induced on a top surface of the metal layer until the sacrificial layer is exposed, and simultaneously removing the metal layer and the sacrificial layer at a second removal rate without substantially removing the hard mask.

Abstract: Slurries for use in the chemical mechanical polishing (CMP) of copper and copper diffusion barriers that reduce pattern sensitive erosion of an underlying dielectric layer include at least one surfactant. Inclusion of surfactants, such as cetyltrimethylammonium bromide in a slurry mixture can reduce pattern sensitive erosion of dielectric materials such as silicon oxide, and fluorinated oxides of silicon that would otherwise occur during CMP of copper and copper diffusion barriers as is typical in the formation of copper interconnect lines in integrated circuits.

Abstract: Slurries for use in the chemical mechanical polishing (CMP) of copper and copper diffusion barriers that reduce pattern sensitive erosion of an underlying dielectric layer include at least one surfactant. Inclusion of surfactants, such as cetyltrimethylammonium bromide in a slurry mixture can reduce pattern sensitive erosion of dielectric materials such as silicon oxide, and fluorinated oxides of silicon that would otherwise occur during CMP of copper and copper diffusion barriers as is typical in the formation of copper interconnect lines in integrated circuits.

Abstract: Slurries and methods for the chemical mechanical polishing of high density copper interconnects in a low k ILD are presented. In a particular embodiment of the present invention, a slurry for polishing copper is formed by combining a surfactant comprising an alkyl ethoxy organic acid such as glycolic acid ethoxylate lauryl ether (GAELE), an abrasive such as silica, an oxidizing agent such as hydrogen peroxide, and a chelating buffer system such as citric acid and potassium citrate dissolved in the mixture. This slurry provides a very low incidence of bent line defects, a low erosion rate, and a low dishing rate on a substrate comprising high density copper interconnects in a low k ILD. Embodiments of methods of the present invention use the disclosed slurries.

Abstract: The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer.

Abstract: A slurry for copper polishing has a pH between 7.5 and 12. In a particular embodiment of the present invention, a slurry for polishing copper has a pH between 8 and 11.5, and includes a SiO2 abrasive, a (NH4)2S2O8 oxidizer, a benzotriazole corrosion inhibitor, and a K3PO4/K2HPO4 buffer. A copper polish slurry, in accordance with the present invention, operates with a high pH of greater than approximately 7.5. In this range the slurry has a low static etch due to formation of a robust, protective layer. This slurry may additionally have S2O8−2 or Fe(CN)6−3 as an oxidizer and can thus offer a high polish rate on the order of 7,000 to 10,000 angstroms per minute which does not decrease significantly during polishing. Such an inventive slurry offers a wide CMP process window such that the slurry and process parameters can be optimized to yield low recess, erosion, and dishing on patterned wafers.

Abstract: The invention provides a chemical-mechanical polishing slurry comprising a liquid, cerium ions as an oxidizer, an abrasive, and a pH increasing substance. The cerium ions are in the liquid in a quantity equal to the inclusion of at least 0.02 molar ammonium cerium nitrate in the liquid. The abrasive is also included in the liquid. The liquid, the cerium ions and the abrasive jointly have a first pH value. The pH increasing substance increases the first pH value to a second pH value above 1.5.