Abstract: A method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language, which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model in order to create a verification platform. In a transmission mode, an autonomous circuit emulator is created by replacing the model in a low level programming language physically describing the circuit to be validated with a high level description generating response data in accordance with the functional specification of the design as a function of stimuli received. A verification mode includes integration of the software model in low level language of the circuit resulting from the design into a verification platform, and creation of a connection of a previously validated autonomous circuit emulator to the interfaces of the software model.

Abstract: The present invention relates to a method for on demand functional verification of a software model of an application specific integrated circuit (ASIC), in a low-level programming language (for example of the HDL type), which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model of the circuit in order to create a verification platform. The method for verification comprises a transmission mode and a verification mode. In the transmission mode an autonomous circuit emulator (1), is created or obtained by replacing the model in a low level programming language physically describing the circuit under design to be validated with a high level (for example C++) abstract description generating response data structures in accordance with the functional specification (20) of the design as a function of the stimuli received.

Abstract: The present invention concerns a method for the functional verification of a software model (40) of an integrated circuit on demand (ASIC), in a low-level language (for example of the HDL type), which separately handles the creation of the model and the debugging of the functional verification tests to be applied to the model of the circuit in order to create a verification platform, comprising the following two steps:

Abstract: An interconnection interface for transmitting digital data between a sending module and a receiving module connected to one another through point-to-point serial links, forming a global data link. Each of the modules are provided, firstly, with a multiplexing unit associated with each of the serial links disposed in the module's physical layer, so as to distribute data transmitted through the global link at a speed determined by the sending module to a given number of parallel links, with each of these parallel links conveying a part of the transmitted data at a speed higher than the sending module data speed; and secondly, with a demultiplexing unit associated to the parallel links conveying received data parts, so as to synchronously and integrally reconstitute these received data parts at a speed accepted by the receiving module.

Abstract: A process and interface for interconnection of multiprocessor modules by point-to-point serial-to-parallel links. Data processing or data communication modules (A and B) are interconnected by means of high-speed point-to-point serial links conveying multiplexed information organized into frames comprising a start-of-frame recognition pattern. The process, on transmission and on reception, performs an analog synchronization of the basic clocks of the modules to a reference clock generated by one of the modules designated as a reference module, called the master module, the other modules being called slave modules, and a digital synchronization of the start-of-frame of each slave module to the start-of-frame sent by the master module.

Abstract: A videoconferencing center (31, 33) for data communications and teleprocessing is provided which comprises first routing switches having a plurality of sending ports (51, 53, 55, 57) and a plurality of receiving ports (50, 52, 54, 56), each sending port adapted to be operatively connected to a receiving data terminal equipment unit (10, 28, 29) or to a receiving port of second routing switch (32, 34), each receiving port adapted to be operatively connected to a sending data terminal equipment unit (10, 28, 29) or to a sending port of another group switching center (32, 34). Each receiving port is assigned a receiving stack (102) that is addressable in a single logical address space and each sending port is assigned a sending stack (103) for containing addresses of said single logical address space. The single logical address reduces the risk of losing data received, which risk results from the necessary limits on physical addresses of stacks.