Abstract: An electronic device may include a printed circuit with a surface-mounted component. The component may produce resistive heating within the printed circuit. Resistive thermal devices (RTDs) may be embedded within the printed circuit. An RTD may at least partially overlap the electrical component. The RTD may include contact pads on a flexible substrate and a meandering conductive trace between the contact pads. The trace may have a resistance varying linearly as a function of temperature. A data acquisition system (DAQ) may measure the resistance of the RTD. Control circuitry may identify the temperature of the printed circuit based on the resistance of the RTD measured by the DAQ and may reduce power consumption by the component when the temperature exceeds a threshold. This may serve to prevent overheating in the printed circuit over time, thereby maximizing the operating life of the printed circuit.

Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

Abstract: An electronic device may include a printed circuit with a surface-mounted component. The component may produce resistive heating within the printed circuit. Resistive thermal devices (RTDs) may be embedded within the printed circuit. An RTD may at least partially overlap the electrical component. The RTD may include contact pads on a flexible substrate and a meandering conductive trace between the contact pads. The trace may have a resistance varying linearly as a function of temperature. A data acquisition system (DAQ) may measure the resistance of the RTD. Control circuitry may identify the temperature of the printed circuit based on the resistance of the RTD measured by the DAQ and may reduce power consumption by the component when the temperature exceeds a threshold. This may serve to prevent overheating in the printed circuit over time, thereby maximizing the operating life of the printed circuit.

Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

Abstract: An electronic device may include a printed circuit with a surface-mounted component. The component may produce resistive heating within the printed circuit. Resistive thermal devices (RTDs) may be embedded within the printed circuit. An RTD may at least partially overlap the electrical component. The RTD may include contact pads on a flexible substrate and a meandering conductive trace between the contact pads. The trace may have a resistance varying linearly as a function of temperature. A data acquisition system (DAQ) may measure the resistance of the RTD. Control circuitry may identify the temperature of the printed circuit based on the resistance of the RTD measured by the DAQ and may reduce power consumption by the component when the temperature exceeds a threshold. This may serve to prevent overheating in the printed circuit over time, thereby maximizing the operating life of the printed circuit.

Abstract: An electronic device may include a printed circuit with a surface-mounted component. The component may produce resistive heating within the printed circuit. Resistive thermal devices (RTDs) may be embedded within the printed circuit. An RTD may at least partially overlap the electrical component. The RTD may include contact pads on a flexible substrate and a meandering conductive trace between the contact pads. The trace may have a resistance varying linearly as a function of temperature. A data acquisition system (DAQ) may measure the resistance of the RTD. Control circuitry may identify the temperature of the printed circuit based on the resistance of the RTD measured by the DAQ and may reduce power consumption by the component when the temperature exceeds a threshold. This may serve to prevent overheating in the printed circuit over time, thereby maximizing the operating life of the printed circuit.

Abstract: Structures that implement three-dimensional (3D) conductive material (e.g., copper) in printed circuit boards (PCBs) are disclosed. 3D (three-dimensional) conductive material may include trenches and/or buried vias that are filled with conductive material in the PCBs. Trenches may be formed in build-up layers of a PCB by overlapping multiple laser drilled vias. The trenches may be filled with conductive material using electroplating process(es). Buried vias may be formed through the core layers of the PCB by mechanical drilling. The buried via may be filled with solid conductive material using a combination of electroless plating and electrolytic plating of conductive material. Various PCB structures are disclosed that implement combinations of these trenches and/or these buried vias filled with conductive material.

Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.

Abstract: Printed circuit boards having an increased density of vertical interconnect paths, as well as methods for their manufacture. One example may provide a printed circuit board having an increased density of vertical interconnect paths by forming a plurality of segmented vias. The segmented vias may extend through interior layers of the printed circuit board. The segmented vias may be formed of portions of vias in the interior layers of the printed circuit board. An area between three or more segmented vias may be filled with resin or other material or materials.

Abstract: A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads.

Abstract: A routing apparatus includes a PCB having first and second arrays of contact pads, an interposer having third, fourth and fifth arrays of contact pads, the third and fourth arrays of contact pads being disposed on opposing surfaces of the interposer, the third array of contact pads being electrically connected to the first array of contact pads. First and second integrated circuits are respectively mounted on the second and fourth arrays of contact pads. The interposer includes a first group of conductive traces insulated from one another, a first array of conductive vias extending perpendicularly to the first group of conductive traces, the first array of conductive vias including through-vias connecting the third array of contact pads to corresponding contact pads in the fourth array of contact pads.

Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

Abstract: A circuit board includes conductive traces being sandwiched by an upper insulating layer and a lower insulating layer, a first array of conductive vias extending perpendicularly to the conductive traces, the vias in the first array of conductive vias being arranged such that any two adjacent vias in a row of vias extending along any given dimension in the first array of conductive vias are equally spaced from each other, and isolation resistors embedded within the first array of conductive vias such that each isolation resistor is disposed between at least two adjacent vias in the first array of conductive vias, each isolation resistor being disposed closer to the conductive via to which the isolation resistor is coupled than all other conductive vias surrounding the isolation resistor.

Abstract: A printed circuit board may have embedded strain gauges. A strain gauge may be formed from a metal trace on a polymer substrate. The metal trace may form a variable strain gauge resistor that is incorporated into a bridge circuit for a strain gauge. The printed circuit may have a rigid printed circuit layer with a recess that receives the polymer substrate. Metal pads on the polymer substrate may be coupled to respective ends of the variable strain gauge resistor. The rigid printed circuit substrate with the recess may be laminated between additional rigid printed circuit layers. Vias may be formed through the additional rigid printed circuit layers to contact the metal pads. Embedded strain gauges may be used in gathering strain data when strain is imparted to a printed circuit during use of the printed circuit in an electronic device or during testing.

Abstract: A printed circuit board may have embedded strain gauges. A strain gauge may be formed from a metal trace on a polymer substrate. The metal trace may form a variable strain gauge resistor that is incorporated into a bridge circuit for a strain gauge. The printed circuit may have a rigid printed circuit layer with a recess that receives the polymer substrate. Metal pads on the polymer substrate may be coupled to respective ends of the variable strain gauge resistor. The rigid printed circuit substrate with the recess may be laminated between additional rigid printed circuit layers. Vias may be formed through the additional rigid printed circuit layers to contact the metal pads. Embedded strain gauges may be used in gathering strain data when strain is imparted to a printed circuit during use of the printed circuit in an electronic device or during testing.