Abstract: Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.

Abstract: Systems and methods for sampling data at a non-volatile memory system are disclosed. In one implementation, a controller of a non-volatile memory system that is coupled with a host device acquires a read level voltage of a first word line of a memory block of a non-volatile memory of the non-volatile memory system. The controller accesses one or more lookup tables to determine an offset voltage for a second word line of the memory block based on a program/erase count and a read/disturb count associated with the memory block; applies the read level voltage and the offset voltage to the second word line to sample data stored at the memory block; and determines whether the data sampled from the memory block contains errors.

Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.

Abstract: In one embodiment, a memory system is provided comprising a memory die and a controller. The memory die comprises a non-volatile memory, a data latch, and an on-chip randomizer. The controller is configured to send a command to the memory die to cause the on-chip randomizer to store random data in the data latch and send data to the memory die to overwrite some, but not all, of the random data in the data latch, wherein the memory die is configured to transfer the data and random data stored in the data latch to the non-volatile memory. Other embodiments are provided.

Abstract: A memory die is provided comprising a non-volatile memory organized in physical pages, a transfer data latch in communication with the non-volatile memory, at least one auxiliary data latch in communication with the transfer data latch, and circuitry. The circuitry is configured to receive a plurality of sense commands, wherein each sense command indicates a physical page in the non-volatile memory to be sensed and a portion of the physical page to be stored in the at least one auxiliary data latch. For each sense command, the circuitry is configured to store data from the physical page sensed by the sense command in the transfer data latch and move data from the portion of the physical page indicated by the sense command to an available location in the at least one auxiliary data latch.

Abstract: A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed.

Abstract: A non-volatile memory can perform a first operation (such as a write, for example) on a designated group of one or more addressed pages using a first set of data stored in the corresponding set of data latches and also receive a request for a second operation (such as a read, for example) that also uses some of these corresponding data latches with a second set of data. During the first operation, when at least one latch of each set of the corresponding become available for the second operation, the memory whether there are a sufficient number of the corresponding set of data latches to perform the second operation during the first operation; if not, the second operation is delayed.

Abstract: An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in an array is addressable by a column line and a row line. A column address decoder receives a column address signal and selects one or more column lines of each array in response. A row address decoder receives a row address signal and selects a row line of each array in response. The memory device also has a plurality (k) of sense amplifiers, with one sense amplifier associated with each array, connectable to one or more column lines of the array and receives a signal therefrom supplied from an addressed memory cell. The memory device further has a register; and a control circuit.

Abstract: An integrated circuit memory device has an array of memory cells arranged in a plurality of rows and columns and a plurality of row lines and a plurality of column lines. Cells arranged in the same row are connected by a common row line, and cells arranged in the same column are connected by a common column line. Each cell in the array is addressed by an address signal which has a plurality of bits. A sense amplifier circuit is connectable to one or more of the plurality of column lines of the array. An address input terminal receives in series the plurality of bits of the address signal. Each of the column lines is connectable to a pre-charge voltage, in response to a read command.