Abstract: Disclosed herein are techniques for improving the light emitting efficiency of micro light emitting diodes. According to certain embodiments, micro-LEDs having small physical dimensions are fabricated on III-nitride materials with semi-polar crystal lattice orientations to reduce the surface recombination of excess charge carriers that does not generate photons and to reduce the polarization induced internal field that may cause energy band shift and aggravate the Quantum-Confined Stark Effect, thereby increasing the peak quantum efficiencies and/or reducing the peak efficiency current density of the micro-LEDs.

Abstract: An optical system includes an optical waveguide, a micro light emitting diode (micro-LED) configured to emit at least partially polarized light, and a waveguide coupler configured to couple the at least partially polarized light from the micro-LED into the optical waveguide with a coupling efficiency higher than a coupling efficiency of the waveguide coupler for unpolarized light. The micro-LED includes a substrate including a hexagonal lattice and having a first surface parallel to a semi-polar plane of the hexagonal lattice, and a plurality of layers grown on the first surface. The plurality of layers includes an active layer that includes a III-nitride material and has a top surface parallel to the semi-polar plane and the first surface of the substrate, such that the light emitted by the micro-LED is at least partially polarized and can be more efficiently coupled into the optical waveguide.

Abstract: Disclosed herein are techniques for improving performance of micro light emitting diodes. According to certain embodiments, a semi-polar-oriented light emitting diode (LED) (e.g., grown on (2021) plane or (1122) plane) includes a buried p-GaN layer that is grown before the active region and the n-GaN layer of the LED are grown, such that the polarization-induced (including strain-induced piezoelectric polarization and spontaneous polarization) electrical field and the built-in depletion field in the active region are in opposite directions during normal operations, thereby reducing or minimizing the overall internal electric field that can contribute to Quantum-Confined Stark Effect. The buried p-GaN layer is grown on an n-i-n sacrificial etch junction, which can be laterally wet-etched to separate the semi-polar-oriented LED from the underlying substrate and expose the p-GaN layer for planar or vertical (rather than horizontal or lateral) activation.

Abstract: A light emitting diode (LED) is manufactured using a process in which hydrogen diffuses out of a p-doped semiconductor layer via an exposed side wall of the p-doped semiconductor layer. The process includes forming a light generation layer on a base semiconductor layer and forming the p-doped semiconductor layer on the light generation layer. A tunnel junction layer is formed on the p-doped semiconductor layer and a contact layer is formed on the junction layer. The process also includes etching through at least the contact layer, the tunnel junction layer, and the p-doped semiconductor layer to expose the side wall of the p-doped semiconductor layer and enabling hydrogen to diffuse out of the p-doped semiconductor layer at least partially through the exposed side wall.

Abstract: In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower forward voltage than a conventional bonded interface. Reducing the absorption and/or the forward voltage in a device may improve the efficiency of the device.

Abstract: A device includes a semiconductor structure with at least one III-P light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further includes a GaAsxP1-x p-contact layer, wherein x<0.45. A first metal contact is in direct contact with the GaAsxP1-x p-contact layer. A second metal contact is electrically connected to the n-type region. The first and second metal contacts are formed on a same side of the semiconductor structure.

Abstract: In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower forward voltage than a conventional bonded interface. Reducing the absorption and/or the forward voltage in a device may improve the efficiency of the device.

Abstract: In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower forward voltage than a conventional bonded interface. Reducing the absorption and/or the forward voltage in a device may improve the efficiency of the device.

Abstract: A device includes a semiconductor structure with at least one III-P light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further includes a GaAsxP1-x p-contact layer, wherein x<0.45. A first metal contact is in direct contact with the GaAsxP1-x p-contact layer. A second metal contact is electrically connected to the n-type region. The first and second metal contacts are formed on a same side of the semiconductor structure.

Abstract: A device includes a semiconductor structure with at least one III-P light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further includes a GaAsxP1?x p-contact layer, wherein x<0.45. A first metal contact is in direct contact with the GaAsxP1?x p-contact layer. A second metal contact is electrically connected to the n-type region. The first and second metal contacts are formed on a same side of the semiconductor structure.

Abstract: A semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. At least 10% of a thickness of the semiconductor structure on the first side of the light emitting region comprises indium. Some examples of such a semiconductor light emitting device may be formed by growing an n-type region, growing a p-type region, and growing a light emitting layer disposed between the n-type region and the p-type region. The difference in temperature between the growth temperature of a part of the n-type region and the growth temperature of a part of the p-type region is at least 140° C.

Abstract: A semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. At least 10% of a thickness of the semiconductor structure on the first side of the light emitting region comprises indium. Some examples of such a semiconductor light emitting device may be formed by growing an n-type region, growing a p-type region, and growing a light emitting layer disposed between the n-type region and the p-type region. The difference in temperature between the growth temperature of a part of the n-type region and the growth temperature of a part of the p-type region is at least 140° C.

Abstract: A device includes a semiconductor structure with at least one III-P light emitting layer disposed between an n-type region and a p-type region. The semiconductor structure further includes a GaAsxP1-x p-contact layer, wherein x<0.45. A first metal contact is in direct contact with the GaAsxP1-x p-contact layer. A second metal contact is electrically connected to the n-type region. The first and second metal contacts are formed on a same side of the semiconductor structure.

Abstract: In some embodiments of the invention, a transparent substrate AlInGaP device includes an etch stop layer that may be less absorbing than a conventional etch stop layer. In some embodiments of the invention, a transparent substrate AlInGaP device includes a bonded interface that may be configured to give a lower forward voltage than a conventional bonded interface. Reducing the absorption and/or the forward voltage in a device may improve the efficiency of the device.

Abstract: A semiconductor structure includes a light emitting region, a p-type region disposed on a first side of the light emitting region, and an n-type region disposed on a second side of the light emitting region. At least 10% of a thickness of the semiconductor structure on the first side of the light emitting region comprises indium. Some examples of such a semiconductor light emitting device may be formed by growing an n-type region, growing a p-type region, and growing a light emitting layer disposed between the n-type region and the p-type region. The difference in temperature between the growth temperature of a part of the n-type region and the growth temperature of a part of the p-type region is at least 140° C.

Abstract: In a III-nitride light emitting device, a ternary or quaternary light emitting layer is configured to control the degree of phase separation. In some embodiments, the difference between the InN composition at any point in the light emitting layer and the average InN composition in the light emitting layer is less than 20%. In some embodiments, control of phase separation is accomplished by controlling the ratio of the lattice constant in a relaxed, free standing layer having the same composition as the light emitting layer to the lattice constant in a base region. For example, the ratio may be between about 1 and about 1.01.

Abstract: In a III-nitride light emitting device, a ternary or quaternary light emitting layer is configured to control the degree of phase separation. In some embodiments, the difference between the InN composition at any point in the light emitting layer and the average InN composition in the light emitting layer is less than 20%. In some embodiments, control of phase separation is accomplished by controlling the ratio of the lattice constant in a relaxed, free standing layer having the same composition as the light emitting layer to the lattice constant in a base region. For example, the ratio may be between about 1 and about 1.01.

Abstract: In a III-nitride light emitting device, a ternary or quaternary light emitting layer is configured to control the degree of phase separation. In some embodiments, the difference between the InN composition at any point in the light emitting layer and the average InN composition in the light emitting layer is less than 20%. In some embodiments, control of phase separation is accomplished by controlling the ratio of the lattice constant in a relaxed, free standing layer having the same composition as the light emitting layer to the lattice constant in a base region. For example, the ratio may be between about 1 and about 1.01.

Abstract: III-Nitride light emitting diodes having improved performance are provided. In one embodiment, a light emitting device includes a substrate, a nucleation layer disposed on the substrate, a defect reduction structure disposed above the nucleation layer, and an n-type III-Nitride semiconductor layer disposed above the defect reduction structure. The n-type layer has, for example, a thickness greater than about one micron and a silicon dopant concentration greater than or equal to about 1019 cm−3. In another embodiment, a light emitting device includes a III-Nitride semiconductor active region that includes at least one barrier layer either uniformly doped with an impurity or doped with an impurity having a concentration graded in a direction substantially perpendicular to the active region.

Abstract: III-Nitride light emitting diodes having improved performance are provided. In one embodiment, a light emitting device includes a substrate, a nucleation layer disposed on the substrate, a defect reduction structure disposed above the nucleation layer, and an n-type III-Nitride semiconductor layer disposed above the defect reduction structure. The n-type layer has, for example, a thickness greater than about one micron and a silicon dopant concentration greater than or equal to about 1019 cm−3. In another embodiment, a light emitting device includes a III-Nitride semiconductor active region that includes at least one barrier layer either uniformly doped with an impurity or doped with an impurity having a concentration graded in a direction substantially perpendicular to the active region.