Patents by Inventor Annelies Delabie
Annelies Delabie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11476119Abstract: A method for manufacturing a semiconductor structure that comprises providing a monocrystalline silicon base layer comprising a first region for manufacturing the III-N semiconductor device and a second region for manufacturing the silicon semiconductor device; providing on the monocrystalline silicon base layer a mask layer, the mask layer being interrupted, in the first region, by a recess in the monocrystalline silicon base layer, wherein the mask layer comprises a 2D material; forming, selectively, a layer of gamma-Al2O3 at the bottom of the recess by a first growth process; forming, selectively on the layer of gamma-Al2O3, a III-N semiconductor device stack by a second growth process, and thereafter; manufacturing, in the second region, at least partially a silicon semiconductor device.Type: GrantFiled: July 14, 2021Date of Patent: October 18, 2022Assignee: IMEC VZWInventors: Ming Zhao, Annelies Delabie
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Publication number: 20220020587Abstract: A method for manufacturing a semiconductor structure that comprises providing a monocrystalline silicon base layer comprising a first region for manufacturing the III-N semiconductor device and a second region for manufacturing the silicon semiconductor device; providing on the monocrystalline silicon base layer a mask layer, the mask layer being interrupted, in the first region, by a recess in the monocrystalline silicon base layer, wherein the mask layer comprises a 2D material; forming, selectively, a layer of gamma-Al2O3 at the bottom of the recess by a first growth process; forming, selectively on the layer of gamma-Al2O3, a III-N semiconductor device stack by a second growth process, and thereafter; manufacturing, in the second region, at least partially a silicon semiconductor device.Type: ApplicationFiled: July 14, 2021Publication date: January 20, 2022Inventors: Ming Zhao, Annelies Delabie
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Publication number: 20200111892Abstract: According to an aspect of the disclosed technology, a method for forming a gate of a semiconductor device is disclosed. The method includes depositing a sacrificial material to form a preliminary sacrificial gate fill structure, etching back an upper surface of the preliminary sacrificial gate fill structure to obtain a final sacrificial gate fill structure, and replacing the sacrificial material of the final sacrificial gate fill structure with a conductive gate fill material by a conversion reaction, thereby forming a gate electrode of the semiconductor device. By replacing the sacrificial material with a conductive gate fill material rather than depositing and subsequently etching a conductive gate fill layer, surface of the conductive gate fill material is made relatively smooth.Type: ApplicationFiled: October 9, 2019Publication date: April 9, 2020Inventors: Boon Teik Chan, Efrain Altamirano Sanchez, Annelies Delabie, Yoann Tomczak
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Patent number: 10056253Abstract: Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. The first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material. The example method includes providing the first nanostructure on a substrate. The method also includes forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface. The method further includes forming the second nanostructure by a vapor deposition process. The second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.Type: GrantFiled: June 7, 2017Date of Patent: August 21, 2018Assignee: IMEC VZWInventors: Annelies Delabie, Silvia Armini
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Patent number: 9984874Abstract: Method of producing one or more transition metal dichalcogenide (MX2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.Type: GrantFiled: December 18, 2014Date of Patent: May 29, 2018Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Matty Caymax, Markus Heyne, Annelies Delabie
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Patent number: 9842734Abstract: A method is provided for forming a feature of a target material on a substrate. The method including: forming a feature of a sacrificial material on the substrate; and forming the feature of the target material by a deposition process during which the feature of the sacrificial material is removed from the substrate by forming a volatile reaction product with a precursor of the deposition process, wherein the sacrificial material is replaced by the target material and the target material is selectively deposited on surface portions of the substrate, which portions were covered by the feature of the sacrificial material, to form the feature of the target material.Type: GrantFiled: December 14, 2016Date of Patent: December 12, 2017Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Annelies Delabie, Markus Heyne
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Publication number: 20170352766Abstract: Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. The first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material. The example method includes providing the first nanostructure on a substrate. The method also includes forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface. The method further includes forming the second nanostructure by a vapor deposition process. The second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.Type: ApplicationFiled: June 7, 2017Publication date: December 7, 2017Applicant: IMEC VZWInventors: Annelies Delabie, Silvia Armini
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Publication number: 20170250075Abstract: Method of producing one or more transition metal dichalcogenide (MX2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.Type: ApplicationFiled: December 18, 2014Publication date: August 31, 2017Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Matty Caymax, Markus Heyne, Annelies Delabie
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Publication number: 20170178905Abstract: A method is provided for forming a feature of a target material on a substrate. The method including: forming a feature of a sacrificial material on the substrate; and forming the feature of the target material by a deposition process during which the feature of the sacrificial material is removed from the substrate by forming a volatile reaction product with a precursor of the deposition process, wherein the sacrificial material is replaced by the target material and the target material is selectively deposited on surface portions of the substrate, which portions were covered by the feature of the sacrificial material, to form the feature of the target material.Type: ApplicationFiled: December 14, 2016Publication date: June 22, 2017Applicants: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVEN, KU LEUVEN R&DInventors: Annelies Delabie, Markus Heyne
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Patent number: 9041164Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.Type: GrantFiled: February 19, 2014Date of Patent: May 26, 2015Assignee: IMECInventors: Roel Gronheid, Christoph Adelmann, Annelies Delabie, Gustaf Winroth
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Patent number: 9028623Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.Type: GrantFiled: February 20, 2014Date of Patent: May 12, 2015Assignee: IMECInventors: Annelies Delabie, Matty Caymax
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Patent number: 8921228Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.Type: GrantFiled: October 3, 2012Date of Patent: December 30, 2014Assignee: IMECInventors: Johan Swerts, Sven Van Elshocht, Annelies Delabie
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Publication number: 20140239461Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.Type: ApplicationFiled: February 20, 2014Publication date: August 28, 2014Applicant: IMECInventors: Annelies Delabie, Matty Caymax
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Publication number: 20140231968Abstract: In one aspect, a method is disclosed that includes providing a substrate having a topography that comprises a relief and providing an anti-reflective film conformally over the substrate using a molecular layer deposition step. The anti-reflective film may be formed of a compound selected from the group consisting of: (i) an organic compound chemically bound to an inorganic compound, where one of the organic compound and the inorganic compound is bound to the substrate and where the organic compound absorbs light at at least one wavelength selected in the range 150-500 nm, or (ii) a monodisperse organic compound absorbing light at at least one wavelength selected in the range 150-500 nm. The method further includes providing a photoresist layer on the anti-reflective film.Type: ApplicationFiled: February 19, 2014Publication date: August 21, 2014Applicant: IMECInventors: Roel Gronheid, Christoph Adelmann, Annelies Delabie, Gustaf Winroth
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Patent number: 8007865Abstract: One inventive aspect is related to an atomic layer deposition (ALD) method comprising: a) providing a semiconductor substrate in a reactor, b) providing a pulse of a first precursor gas into the reactor at a first temperature, c) providing a first pulse of a second precursor gas into the reactor at a second temperature, and d) providing a second pulse of the second precursor gas at a third temperature lower than the second temperature. Another inventive aspect relates to a reactor suitable to apply the method.Type: GrantFiled: May 31, 2006Date of Patent: August 30, 2011Assignee: IMECInventors: Annelies Delabie, Matty Caymax
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Patent number: 7927933Abstract: The present invention relates generally to integrated circuit (IC) fabrication processes. The present invention relates more particularly to the treatment of surfaces, such as silicon dioxide or silicon oxynitride layers, for the subsequent deposition of a metal, metal oxide, metal nitride and/or metal carbide layer. The present invention further relates to a high-k gate obtainable by a method of the invention.Type: GrantFiled: February 16, 2005Date of Patent: April 19, 2011Assignees: IMEC, ASM International, Renesas Technology CorporationInventors: Jan Willem Maes, Annelies Delabie, Yashuhiro Shimamoto
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Patent number: 7579285Abstract: The invention is related to an ALD method for depositing a layer including the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.Type: GrantFiled: July 10, 2006Date of Patent: August 25, 2009Assignee: IMECInventors: Paul Zimmerman, Matty Caymax, Stefan De Gendt, Annelies Delabie, Lars-Ake Ragnarsson
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Publication number: 20070049045Abstract: The invention is related to an ALD method for depositing a layer comprising the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.Type: ApplicationFiled: July 10, 2006Publication date: March 1, 2007Inventors: Paul Zimmerman, Matty Caymax, Stefan Gendt, Annelies Delabie, Lars-Ake Ragnarsson
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Publication number: 20060286810Abstract: One inventive aspect is related to an atomic layer deposition (ALD) method comprising: a) providing a semiconductor substrate in a reactor, b) providing a pulse of a first precursor gas into the reactor at a first temperature, c) providing a first pulse of a second precursor gas into the reactor at a second temperature, and d) providing a second pulse of the second precursor gas at a third temperature lower than the second temperature. Another inventive aspect relates to a reactor suitable to apply the method.Type: ApplicationFiled: May 31, 2006Publication date: December 21, 2006Inventors: Annelies Delabie, Matty Caymax
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Publication number: 20060180879Abstract: The present invention relates generally to integrated circuit (IC) fabrication processes. The present invention relates more particularly to the treatment of surfaces, such as silicon dioxide or silicon oxynitride layers, for the subsequent deposition of a metal, metal oxide, metal nitride and/or metal carbide layer. The present invention further relates to a high-k gate obtainable by a method of the invention.Type: ApplicationFiled: February 16, 2005Publication date: August 17, 2006Inventors: Jan Maes, Annelies Delabie, Yashuhiro Shimamoto