Abstract: A power semiconductor device includes a semiconductor body and a first terminal at the semiconductor body. The first terminal has a first side for adjoining an encapsulation and a second side for adjoining the semiconductor body. The first terminal includes, at the first side, a top layer; and, at the second side, a base layer coupled with the top layer, wherein a sidewall of the top layer and/or a sidewall of the base layer is arranged in an angle smaller than 85° with respect to a plane.

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

Abstract: An integrated circuit device including a chip die having a first area with a first thickness surrounding a second area with a second thickness, the first thickness is greater than the second thickness, the chip die having a front-side and a back-side, at least one passive electrical component provided at least one of in or over the chip die in the first area on the front-side, and at least one active electrical component provided at least one of in or over the chip die in the second area on the front-side.

Abstract: In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer.

Abstract: A process for making a photovoltaic cell includes providing a semiconducting substrate having a back side passivation layer, and coating a self-assembling emulsion that includes glass frit particles onto the back side passivation layer. The emulsion is allowed to self-assemble into a network of traces that define cells. An electrode is formed over the network to create a precursor cell, which is then fired to cause the network to burn through the passivation layer and establish electrical contact between the semiconducting substrate and the electrode.

Abstract: The present invention refers to an electrode comprising a first metallic layer and a compound comprising at least one of a nitride, oxide, and oxynitride of a second metallic material.

Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Abstract: The invention refers to a selective deposition method. A substrate comprising at least one structured surface is provided. The structured surface comprises a first area and a second area. The first area is selectively passivated regarding reactants of a first deposition technique and the second area is activated regarding the reactants the first deposition technique. A passivation layer on the second area is deposited via the first deposition technique. The passivation layer is inert regarding a precursors selected from a group of oxidizing reactants. A layer is deposited in the second area using a second atomic layer deposition technique as second deposition technique using the precursors selected form the group of oxidizing reactants.

Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Abstract: Fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected thereto on one side through a buried contact, in particular, for a semiconductor memory cell with a planar selection transistor in the substrate and connected through the buried contact, includes providing a trench using an opening in a hard mask, providing a capacitor dielectric in lower and central trench regions, the collar in central and upper trench regions, and a conductive filling at least as far as the insulation collar topside, completely filling the trench with a filling material, carrying out STI trench fabrication process, removing the filling material and sinking the filling to below the collar topside, forming an insulation region on one side above the collar; uncovering a connection region on a different side above the collar, and forming the buried contact by depositing and etching back a metallic filling.

Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

Abstract: A semiconductor substrate is provided, on which there is arranged a first layer, a second layer and a third layer. The third layer is, for example, a resist mask that is used to pattern the second layer. The second layer is, for example, a patterned hard mask used to pattern the first layer. Then, the third layer is removed and a fourth layer is deposited. The fourth layer is, for example, an insulator that fills the trenches which have been formed in the first layer. Then, the fourth layer is planarized by a CMP step. The planarization is continued and the second layer, which is, for example, a hard mask, is removed from the first layer together with the fourth layer. The fourth layer remains in place in a trench which is arranged in the first layer.

Abstract: The invention provides methods which can be used to structure even precious metal electrodes with conventional CMP steps, in particular with the aid of conventional slurries such as are already used to structure non-precious metals. Owing to the formation of an alloy, the chemically active components of the slurry are capable of attacking the additive to the precious metal in the alloy, as a result of which the surface of the alloy layer is roughened and the mechanical removal of the precious metal is increased.

Abstract: The present invention relates to a novel method for fabricating a storage capacitor designed as a trench or a stacked capacitor and is used in particular in a DRAM memory cell. The method includes steps of forming a lower, metallic capacitor electrode, a storage dielectric and an upper capacitor electrode. The lower, metallic capacitor electrode is formed in a self-aligned manner on a silicon base material in such a way that uncovered silicon regions are first produced at locations at which the lower capacitor electrode will be formed, and then metal silicide is selectively formed on the uncovered silicon regions.

Abstract: A trench capacitor for use in a DRAM memory cell contains a lower capacitor electrode, a storage dielectric, and an upper capacitor electrode, which are at least partially disposed in a trench. The lower capacitor electrode adjoins, in a lower trench region, a wall of the trench, while in the upper trench region there is a spacer layer that adjoins a wall of the trench and is made from an insulating material. The upper electrode contains at least three layers, a first layer disposed in the trench on the storage dielectric and containing doped polysilicon, a second layer disposed on the first layer and containing metal-silicide, and a third layer disposed on the second layer and containing doped polysilicon. The layers of the upper electrode in each case extending along the walls and the base of the trench up to at least the upper edge of the spacer layer.

Abstract: The invention relates to a method for production of a metallic or metal-containing layer (5) by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon- or germanium-containing layer before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements or the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.

Abstract: Memory cell arrangement having a memory cell array which has at least one layer of magnetoresistive memory components (11) which are each connected to first contact-making lines (10), the first contact-making lines (10) lying within a first dielectric layer (6), and are each connected to second contact-making lines (20; 29; 35), the second contact-making lines (20; 29; 35) lying within a second dielectric layer (17; 27; 32).

Abstract: An upper capacitor electrode of a trench capacitor of a DRAM memory cell is formed at least in part as a result of a plurality of metal-containing layers being deposited one on top of another and in each case being conditioned after they have been deposited. In this way, the internal stress of the electrode layer can be reduced, and therefore a breaking strength and a resistance to leakage currents of the trench capacitor can be increased.

Abstract: The ALD process chamber has heating radiation sources and the process sequence includes rapid temperature changes on a substrate surface of a substrate arranged in the ALD process chamber. The temperature changes are controlled and the ALD and CVD processes are optimized by in situ temperature steps, for example in order to produce nanolaminates.

Abstract: The invention discloses a method for the chemical-mechanical polishing of layers composed of metals of the group of platinum metals, particularly iridium. In the CMP process, high erosion rates for iridium and a high selectivity relative to silicon oxide are achieved upon employment of a polishing fluid that contains 1 through 6% by weight abrasive particles, 2 through 20% by weight of at least one oxidation agent selected from the group comprising Ce(IV) salts, salts of chloric acid, salts of peroxodisulfuric acid, hydrogen peroxide and salts of hydrogen peroxide, and 74 through 97% by weight water. This enables the structuring of iridium layers with the assistance of an oxide mask and a CMP process.