Abstract: A programmable compensated digital delay circuit is described in a design format that is suited for integrated circuitry utilizing complementary MOS technology. In the integrated circuit delay, a precise single element is provided that spans a wide delay range. The element has multiple time delay cells that are selectively interconnectable to form one or more delay lines. Each time delay cell has controllable capacitive elements and current sources which, in turn, are selected by use of a nonvolatile memory. Both the capacitive elements and the current sources are arrayed in a binary weighted manner. The delay is set by using portions of the memory to select capacitive elements and current sources. With the memory functioning with other integrated circuitry, different capacitive elements and current sources are switched into and out of the circuit. The programmable compensated digital delay circuit of the invention is self-compensating for temperature and power supply variations.

Abstract: The disclosed device is a programmable compensated digital delay circuit which has a design format suited for integrated circuitry utilizing complementary MOS technology. In the device, a signal-to-be-delayed is provided to the time delay cells which, are selectively interconnectable, for forming one or more delay configurations. In each delay cell, selectable capacitive elements are arrayed in a weighted manner and a memory programmably selects the capacitive elements by switching differently rated capacitive elements into and out of the circuit. Also, selectable current sources are arrayed in a weighted manner, and another memory programmably selects the current sources by switching differently rated current sources into and out of the circuit. The device further includes internal compensation, and, uses a ring oscillator for temperature and power supply compensation. The ring oscillator is formed from a plurality of time delay cells selected for interchangeability with the delay cells.