Abstract: Methods for treating B-cell malignancies such as relapsed and/or refractory B-cell malignancies with a population of genetically engineered T cells expressing a chimeric antigen receptor (CAR) targeting CD19 and having multiple genetic edits, including a disrupted TRAC gene, a disrupted ?2M gene, a disrupted Regnase 1 gene, and/or a disrupted TGFBRII gene.

Abstract: A turbocharger turbine wheel can include a hub that includes a rotational axis, a backdisk and a nose, where the rotational axis defines an axial coordinate (z) in a cylindrical coordinate system that includes a radial coordinate (r) and an azimuthal coordinate (?) in a direction of intended rotation about the rotational axis; and blades that extend outwardly from the hub, where each of the blades includes a leading edge and a trailing edge, where the leading edge includes a lower axial point defined by a first theta angle and an upper axial point defined by a second theta angle, where the first theta angle is greater than the second theta angle with respect to the direction of intended rotation of the turbine wheel.

Abstract: A turbocharger turbine wheel can include a hub that includes a rotational axis, a backdisk and a nose, where the rotational axis defines an axial coordinate (z) in a cylindrical coordinate system that includes a radial coordinate (r) and an azimuthal coordinate (?) in a direction of intended rotation about the rotational axis; and blades that extend outwardly from the hub, where each of the blades includes a leading edge and a trailing edge, where the leading edge includes a lower axial point defined by a first theta angle and an upper axial point defined by a second theta angle, where the first theta angle is greater than the second theta angle with respect to the direction of intended rotation of the turbine wheel.

Abstract: A turbocharger turbine wheel can include a hub that includes a rotational axis, a backdisk and a nose, where the rotational axis defines an axial coordinate (z) in a cylindrical coordinate system that includes a radial coordinate (r) and an azimuthal coordinate (?) in a direction of intended rotation about the rotational axis; and blades that extend outwardly from the hub, where each of the blades includes an inducer portion and an exducer portion, where, in the inducer portion, in a direction outwardly from the hub, each of the blades includes positive lean angles, a zero lean angle and negative lean angles and where, in the exducer portion, in a direction outwardly from the hub, each of the blades includes negative lean angles, a zero lean angle and positive lean angles.

Abstract: A two-sided turbocharger compressor wheel and a housing forming a diffuser for the compressor. A first side and a second side of the compressor wheel are characterized by different values of a trim and of an annulus area. A first side of the diffuser surrounds the first side of the compressor wheel, and a second side of the diffuser surrounds the second side of the compressor wheel. The first and second sides of the diffuser are characterized by different annulus area ratios. The blades of the first and second sides of the compressor wheel are angularly offset from one another. The compressor wheel is configured for greater flow through the side of the compressor wheel that faces away from a related turbine wheel.

Abstract: A memory compiler includes a processor configured to perform a simulation of an operation of an input stage coupled to an input terminal of a memory circuit, wherein the simulation of the operation of the input stage is performed for various slew rate values at the input terminal to obtain corresponding extrinsic input timing delays. The processor is further configured to perform a simulation of an operation of an output stage coupled to an output terminal of the memory circuit, wherein the simulation of the operation of the output stage is performed for various capacitance loading values at the output terminal to obtain corresponding extrinsic output timing delays. The processor is further configured to perform a simulation of an operation of a section of the memory circuit between the input stage and the output stage to obtain an intrinsic timing delay.

Abstract: A two-sided turbocharger compressor wheel and a housing forming a diffuser for the compressor. A first side and a second side of the compressor wheel are characterized by different values of a trim and of an annulus area. A first side of the diffuser surrounds the first side of the compressor wheel, and a second side of the diffuser surrounds the second side of the compressor wheel. The first and second sides of the diffuser are characterized by different annulus area ratios. The blades of the first and second sides of the compressor wheel are angularly offset from one another. The compressor wheel is configured for greater flow through the side of the compressor wheel that faces away from a related turbine wheel.

Abstract: A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.

Abstract: In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.

Abstract: A memory macro includes a plurality of segments corresponding to a plurality of tracking circuits. Each segment of the plurality of segments thereby corresponds to one tracking circuit of the plurality of tracking circuits. In response to a read operation of a memory cell of a segment, a tracking circuit corresponding to the segment is configured to generate an edge of a tracking signal based on which a first edge of a cell signal associated with the memory cell is generated.

Abstract: A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal.

Abstract: A system includes a first plurality of memory macros and a first tracking circuit associated with a memory macro of the first plurality of memory macros. Each memory macro of the first plurality of memory macros includes a corresponding global control circuit configured to receive a first reset signal. The first tracking circuit is configured to generate the first reset signal.

Abstract: A method includes using a first tracking circuit corresponding to a first set of access ports of a memory macro to cause a signal transition of a first tracking signal based on an edge of a clock signal. Using a second tracking circuit corresponding to a second set of access ports of the memory macro, a signal transition of a second tracking signal is caused based on the edge of the clock signal. A reset signal is generated based on the signal transition of the first tracking signal and the signal transition of the second tracking signal. A read operation or a write operation on the memory macro is performed based on the edge of the clock signal and the reset signal.

Abstract: A circuit comprises a driver, a first capacitive device, and a second capacitive device. The driver has an input node, an output node, and a driver supply voltage node. The first capacitive device has a first terminal and a second terminal. The second capacitive device has a first terminal and a second terminal. The first terminal of the first capacitive device is configured to receive a first signal. The second terminal of the first capacitive device is coupled with the driver supply voltage node. The output of the driver is coupled with a first end of the second capacitive device.

Abstract: A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.

Abstract: A method of designing a semiconductor circuit includes generating a model of the semiconductor circuit. The model includes a functional area corresponding to a first block of the semiconductor circuit, and a loading area corresponding to a second block of the semiconductor circuit, wherein the first block is connected to the second block by a signal line. The method further includes extracting, in the functional area, parasitic parameters of the signal line and a device of the first block. The method further includes extracting, in the loading area, parasitic parameters of the signal line, without extracting parasitic parameters of a device of the second block.

Abstract: A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.

Abstract: A circuit includes a signal generating circuit that generates a pre-charge signal based on a clock signal and a column select signal for a column of memory cells associated with the signal generating circuit. A first state of the pre-charge signal depends on a first state of the column select signal, and the first state of the column select signal corresponds to selection of the column of memory cells. The circuit also includes a charge circuit associated with the signal generating circuit and a first data line coupled to the charge circuit. The charge circuit charges the first data line in response to the first state of the pre-charge signal and allows the first data line to float in response to a second state of the pre-charge signal.

Abstract: In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction.

Abstract: A control circuit includes a data driver, a charge circuit, and a first data line coupled with the data driver and the charge circuit. The charge circuit is configured to charge the first data line when the first data line is selected for accessing a memory cell corresponding to the first data line and to not charge the first data line when the first data line is not selected for accessing the memory cell. The data driver, based on a first control signal, is configured to transfer a signal on the first data line to an output of the data driver.