Patents by Inventor Annie Lum
Annie Lum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11138359Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: August 31, 2020Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20200394355Abstract: A method of fabricating an integrated circuit includes identifying an edge device of a plurality of devices, the plurality of devices being part of a first layout including gate structures and diffusion regions, modifying the first layout resulting in a second layout, and fabricating the integrated circuit based on the second layout. Modifying the first layout resulting in the second layout includes adding a dummy device next to the edge device, the dummy device and the edge device having a shared diffusion region, adding a dummy gate structure next to the dummy device, extending the shared diffusion region to at least the dummy device, and performing a design rule check on the second layout. The performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 10762269Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: GrantFiled: July 1, 2019Date of Patent: September 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20190325104Abstract: A method includes designing a first layout of gate structures and diffusion regions of a plurality of active devices, identifying an edge device of the plurality of active devices, modifying the first layout resulting in a second layout, performing a design rule check on the second layout, and fabricating, based on the second layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. Modifying the first layout includes adding a dummy device next to the edge device, adding a dummy gate structure next to the dummy device and extending a shared diffusion region to at least the dummy device. The dummy device and the edge device have the shared diffusion region. Performing the design rule check considers a gate structure of the dummy device as one of two dummy gate structures next to the edge device.Type: ApplicationFiled: July 1, 2019Publication date: October 24, 2019Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 10339248Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.Type: GrantFiled: December 20, 2017Date of Patent: July 2, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Publication number: 20180113973Abstract: A method includes designing a layout of gate structures and diffusion regions of a plurality of devices, identifying an edge device of the plurality of devices, adding a dummy device next to the edge device and a dummy gate structure next to the dummy device resulting in a modified layout, and fabricating, based on the modified layout, at least one of a photolithography mask or at least one component in a layer of a semiconductor device. The dummy device shares a diffusion region with the edge device. A gate structure of the dummy device is one of two dummy gate structures added next to the edge device.Type: ApplicationFiled: December 20, 2017Publication date: April 26, 2018Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 9852249Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.Type: GrantFiled: July 24, 2013Date of Patent: December 26, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Patent number: 8830782Abstract: A circuit including a memory circuit, the memory circuit includes a first plurality of memory arrays and a first plurality of keepers, each keeper of the first plurality of keepers is electrically coupled with a corresponding one of the first plurality of memory arrays. The memory circuit further includes a first current limiter electrically coupled with and shared by the first plurality of keepers.Type: GrantFiled: March 5, 2013Date of Patent: September 9, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek C. Tao, Young Seog Kim
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Publication number: 20130311964Abstract: A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device.Type: ApplicationFiled: July 24, 2013Publication date: November 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Patent number: 8519444Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.Type: GrantFiled: September 10, 2010Date of Patent: August 27, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek C. Tao, Cheng Hung Lee, Chung-Ji Lu, Hong-Chen Cheng, Vineet Kumar Agrawal, Keun-Young Kim, Pyong Yun Cho
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Patent number: 8406078Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.Type: GrantFiled: February 11, 2011Date of Patent: March 26, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek C. Tao, Young Seog Kim
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Patent number: 8395960Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers.Type: GrantFiled: May 12, 2010Date of Patent: March 12, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Annie Lum, Derek Tao
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Publication number: 20120061764Abstract: The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas.Type: ApplicationFiled: September 10, 2010Publication date: March 15, 2012Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie LUM, Derek C. TAO, Cheng Hung LEE, Chung-Ji LU, Hong-Chen CHENG, Vineet Kumar AGRAWAL, Keun-Young KIM, Pyong Yun CHO
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Publication number: 20110280095Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie LUM, Derek TAO
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Publication number: 20110280096Abstract: A memory circuit includes a first plurality of memory arrays disposed in a column fashion. The memory circuit includes a first plurality of keepers each of which is electrically coupled with a corresponding one of the first plurality of memory arrays. A first current limiter is electrically coupled with and shared by the first plurality of keepers. A first plurality of sector switches each are electrically coupled between the first current limiter and a respective one of the first plurality of keepers.Type: ApplicationFiled: February 11, 2011Publication date: November 17, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Annie LUM, Derek C. TAO, Young Seog KIM
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Patent number: 7782692Abstract: A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.Type: GrantFiled: January 9, 2008Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Derek Tao, Jay Lu, Annie Lum
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Publication number: 20090175099Abstract: A read module for register files includes at least one local I/O module coupled to a memory cell for outputting a value stored in the memory cell; and at least one global bit line driver having an input terminal coupled to the local I/O module, and a output terminal coupled to a global bit line for selectively pre-charging the global bit line at a default voltage in response to a local pre-charge signal, and outputting the value stored in the memory cell to the global bit line when the local pre-charge signal is not asserted.Type: ApplicationFiled: January 9, 2008Publication date: July 9, 2009Inventors: Derek Tao, Jay Lu, Annie Lum