Patents by Inventor Anoop Ramachandra IYER

Anoop Ramachandra IYER has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Faulting address prediction for prefetch target address
    Patent number: 11782845
    Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: October 10, 2023
    Assignee: Arm Limited
    Inventors: Alexander Cole Shulyak, Joseph Michael Pusdesris, Abhishek Raja, Karthik Sundaram, Anoop Ramachandra Iyer, Michael Brian Schinzler, James David Dundas, Yasuo Ishii
  • FAULTING ADDRESS PREDICTION FOR PREFETCH TARGET ADDRESS
    Publication number: 20230176979
    Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.
    Type: Application
    Filed: December 2, 2021
    Publication date: June 8, 2023
    Inventors: Alexander Cole SHULYAK, Joseph Michael PUSDESRIS, . ABHISHEK RAJA, Karthik SUNDARAM, Anoop Ramachandra IYER, Michael Brian SCHINZLER, James David DUNDAS, Yasuo ISHII