Patents by Inventor Anosh B. Davierwalla
Anosh B. Davierwalla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8446188Abstract: An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.Type: GrantFiled: April 19, 2010Date of Patent: May 21, 2013Assignee: QUALCOMM, IncorporatedInventors: Kashyap R. Bellur, Anosh B. Davierwalla, Christian Holenstein
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Patent number: 8228714Abstract: In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.Type: GrantFiled: September 9, 2008Date of Patent: July 24, 2012Assignee: QUALCOMM IncorporatedInventors: Anosh B. Davierwalla, Cheng Zhong, Dongkyu Park, Mohamed Hassan Abu-Rahma, Mehdi Hamidi Sani, Sei Seung Yoon
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Patent number: 8130534Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.Type: GrantFiled: January 8, 2009Date of Patent: March 6, 2012Assignee: QUALCOMM IncorporatedInventors: Mohamed Hassan Abu-Rahma, Seung-Chul Song, Sei Seung Yoon, Dongkyu Park, Cheng Zhong, Anosh B. Davierwalla
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Patent number: 8102720Abstract: In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.Type: GrantFiled: February 2, 2009Date of Patent: January 24, 2012Assignee: QUALCOMM IncorporatedInventors: Hari Rao, Anosh B. Davierwalla, Dongkyu Park, Sei Seung Yoon
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Patent number: 7936590Abstract: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit.Type: GrantFiled: December 8, 2008Date of Patent: May 3, 2011Assignee: QUALCOMM IncorporatedInventors: Dongkyu Park, Anosh B. Davierwalla, Cheng Zhong, Mohamed Hassan Soliman Abu-Rahma, Sei Seung Yoon
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Patent number: 7843264Abstract: An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.Type: GrantFiled: January 29, 2008Date of Patent: November 30, 2010Assignee: QUALCOMM, IncorporatedInventors: Anosh B. Davierwalla, Chul Kyu Lee, Vannam Dang
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Publication number: 20100289537Abstract: An integrated circuit configured for producing a predetermined output in a sequential circuit during power on is disclosed. The integrated circuit includes one or more capacitors coupled to one or more internal nodes. The one or more capacitors charge the internal nodes if a voltage at the power supply node ramps up to a set voltage at or faster than a period of time. The integrated circuit also includes a first transistor coupled to the power supply node. The first transistor produces leakage current that charges one or more internal nodes when the voltage on the power supply node ramps up to the set voltage no faster than the period of time. The integrated circuit also includes an output node. A logical value on the output node is based on a logical value on the charged internal nodes when an input signal to the sequential circuit is not active and the voltage on the power supply node is at the set voltage.Type: ApplicationFiled: April 19, 2010Publication date: November 18, 2010Applicant: QUALCOMM INCORPORATEDInventors: Kashyap R. Bellur, Anosh B. Davierwalla, Christian Holenstein
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Publication number: 20100195379Abstract: In a particular embodiment, a device includes a reference voltage circuit to generate a controlled voltage. The device includes a frequency circuit configured to generate a frequency output signal having a pre-set frequency and a counter to generate a count signal based on the pre-set frequency. The device also includes a delay circuit coupled to receive the count signal and to produce a delayed digital output signal and a latch to generate a pulse. The pulse has a first edge responsive to a write command and a trailing edge formed in response to the delayed digital output signal. In a particular embodiment, the pulse width of the pulse corresponds to an applied current level that exceeds a critical current to enable data to be written to an element of the memory but does not exceed a predetermined threshold.Type: ApplicationFiled: February 2, 2009Publication date: August 5, 2010Applicant: QUALCOMM IncorporatedInventors: Hari Rao, Anosh B. Davierwalla, Dongkyu Park, Sei Seung Yoon
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Publication number: 20100172173Abstract: A system and method to read and write data in magnetic random access memories are disclosed. In a particular embodiment, a device includes a spin transfer torque magnetic tunnel junction (STT-MTJ) element and a transistor with a first gate and a second gate coupled to the STT-MTJ element.Type: ApplicationFiled: January 8, 2009Publication date: July 8, 2010Applicant: QUALCOMM INCORPORATEDInventors: Mohamed Hassan Abu-Rahma, Seung-Chul Song, Sei Seung Yoon, Dongkyu Park, Cheng Zhong, Anosh B. Davierwalla
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Publication number: 20100142303Abstract: Circuits, apparatuses, and methods of interposing a selectable delay in reading a magnetic random access memory (MRAM) device are disclosed. In a particular embodiment, a circuit includes a sense amplifier, having a first input, a second input, and an enable input. A first amplifier coupled to an output of a magnetic resistance-based memory cell and a second amplifier coupled to a reference output of the cell also are provided. The circuit further includes a digitally-controllable amplifier coupled to a tracking circuit cell. The tracking circuit cell includes at least one element that is similar to the cell of the magnetic resistance-based memory. The first input of the sense amplifier is coupled to the first amplifier, the second input of the sense amplifier is coupled to the second amplifier, and the enable input is coupled to the third digitally-controllable amplifier via a logic circuit.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Applicant: QUALCOMM INCORPORATEDInventors: Dongkyu Park, Anosh B. Davierwalla, Cheng Zhong, Mohamed Hassan Soliman Abu-Rahma, Sei Seung Yoon
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Publication number: 20100061144Abstract: In a particular embodiment, a memory device is disclosed that includes a memory cell including a resistance-based memory element coupled to an access transistor. The access transistor has a first oxide thickness to enable operation of the memory cell at an operating voltage. The memory device also includes a first amplifier configured to couple the memory cell to a supply voltage that is greater than a voltage limit to generate a data signal based on a current through the memory cell. The first amplifier includes a clamp transistor that has a second oxide thickness that is greater than the first oxide thickness. The clamp transistor is configured to prevent the operating voltage at the memory cell from exceeding the voltage limit.Type: ApplicationFiled: September 9, 2008Publication date: March 11, 2010Applicant: QUALCOMM INCORPORATEDInventors: Anosh B. Davierwalla, Cheng Zhong, Dongkyu Park, Mohamed Hassan Abu-Rahma, Mehdi Hamidi Sani, Sei Seung Yoon
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Publication number: 20090189694Abstract: An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.Type: ApplicationFiled: January 29, 2008Publication date: July 30, 2009Applicant: QUALCOMM IncorporatedInventors: Anosh B. Davierwalla, Chul Kyu Lee, Vannam Dang