Patents by Inventor An-Ru Andrew Cheng

An-Ru Andrew Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7464357
    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: December 9, 2008
    Assignee: Faraday Technology Corp.
    Inventors: An-Ru Andrew Cheng, Chang-Song Lin, Tzu-Chun Liu, Huan-Yung Tseng
  • Patent number: 7036099
    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
    Type: Grant
    Filed: July 25, 2003
    Date of Patent: April 25, 2006
    Assignee: Faraday Technology Corp.
    Inventors: An-Ru Andrew Cheng, Chang-Song Lin, Tzu-Chun Liu, Huan-Yung Tseng
  • Publication number: 20050022142
    Abstract: An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided by design rules for an assigned routing layer. Since the connection in the assigned routing layer is constrained to a minimum, the scan chain is vulnerable to variations in processes relevant to the assigned routing layer. The scan chain makes it easier to locate processes causing low yield rate of the scan chain.
    Type: Application
    Filed: July 25, 2003
    Publication date: January 27, 2005
    Inventors: An-Ru Andrew Cheng, Chang-Song Lin, Tzu-Chun Liu, Huan-Yung Tseng