Abstract: The present invention is directed to a method for planarizing BARC layer in dual damascene process. For forming a dual damascene interconnect structure, by use of the present invention, a planar topography of the BARC layer is achieved by chemical mechanical polishing. The present invention applies a low temperature to bake the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristic. Then, the BARC layer is planarized by chemical mechanical polishing. Next, a high temperature baking of the BARC layer is provided before coating the photoresist, so formation of the BARC layer is controlled with minimized variation in surface level and has the antireflective characteristic. Thus, the profile distortion on the via and the critical dimension control for the via are improved by patterning the via on a planar and an anti-reflective surface.

Abstract: A process for increasing the line width window in a semiconductor process, which is suitable to be used to increase the line width widow at the time of the exposure of an iso-line pattern under 0.13 &mgr;m. This process includes: first forming a positive photoresist layer on the base, then using the first photomask to conduct the first exposure step on the positive photoresist layer. The first photomask is designed to have at least one main line that is opaque. On each of the two sides of the main line, there is a scattering bar. The width of the two scattering bars is greater than ⅓ of the wavelength of the light source that is used, and less than the width of the main line. The second photomask is used to conduct the second exposure step on the positive photoresist layer. The second photomask is designed to have at least two iso-lines that are pervious to light, and each of the two iso-lines is located at one of the two positions corresponding to the two scattering bars of the first photomask design.

Abstract: A thermal flow photolithographic process. A thermal flow photoresist is provided. A cross-linking agent is added to the thermal flow photoresist to form a high-temperature cross-linking photoresist material. A substrate having an insulation layer thereon is provided. The high-temperature cross-linking photoresist is deposited over the insulation layer. The cross-linked photoresist layer on the insulation layer is exposed to light, chemically developed and then heated to cause thermal flow.

Abstract: The present invention is directed to a method for planarizing BARC layer in dual damascene process. For forming dual damascene interconnect structure, by use of the present invention, a planar topography of BARC layer is achieved by chemical mechanical polishing. The present invention applies low temperature to bake the coated BARC layer before BARC material cross-links and induces the anti-reflective characteristic. Then, the BARC layer is planarized by chemical mechanical polishing. Next, a high temperature baking of BARC layer is provided before coating the photoresist, so the BARC layer is controlled with minimized variation in surface level and has the antireflective characteristic. Thus, the profile distortion on via and the critical dimension control for via are improved by patterning via on a planar and anti-reflective surface.

Abstract: A dynamic random access memory (DRAM) is formed on a semiconductor wafer, the semiconductor wafer including a substrate, a thin film layer positioned on the substrate, and a photoresist layer positioned on the thin film layer. Two exposure processes are employed. The first exposure process forms first exposure regions that are linear and parallel with each other on the photoresist layer. The second exposure process forms second exposure regions that are interlaced with and perpendicular to each other on the photoresist layer. Performing a development process to the wafer removes the first exposure regions and the second exposure regions of the photoresist layer to form an array photoresist layer on the thin film layer. The array photoresist layer functions as a mask to perform an etching process to the thin film layer for forming an array thin film layer, the array thin film layer acting as a storage nodes in the DRAM.

Abstract: The present invention provides a method for improving adhesion of low k materials with adjacent Layer. The method at least includes the following steps. First of all, the semiconductor device is provided, and a cap layer is formed on the semiconductor structure. Then, an adhesion promoter layer is formed on the cap layer by spin coating, and a polymer low dielectric constant layer is formed on the adhesion promoter layer. Next, an HMDS (Hexamethyldisilazane) film is deposited on the low dielectric constant layer, the HMDS film can provide both of inorganic and organic bonds. Finally, an etching stop layer or hardmask inorganic layer is formed on the HMDS film.

Abstract: A method of improving a photoresist profile. After a photoresist layer is developed, a hard bake is performed at a temperature lower than a glass transition temperature of the photoresist layer. The photoresist layer is thus able to reflow, so that the profile can be modified. Or alternatively, the hard bake step can be replace by first performing a hard bake at a temperature higher than the glass transition temperature, followed by performing a flow bake at a temperature lower than the glass transition temperature.

Abstract: An alignment mark design has a metal plateau and a metal material formed over a substrate. The metal plateau is within a first dielectric layer. Openings within a second dielectric layer above the first dielectric layer are filled with a metal material. The metal material and the second dielectric layer alternate so that a part of the exposure light passing through the second dielectric layer between sections of the metal material can be reflected into an alignment system by the metal plateau.

Abstract: A substrate is provided. A first dielectric layer is formed over the substrate by deposition. Etching stop layer and a second dielectric layer are formed in turn over the first dielectric. Next, the second dielectric layer is dealt with Lewis acid. Then, a first photoresist layer is defined and formed over the second dielectric layer. And then dry etching is carried out by means of the first photoresist layer as the mask to form a via hole. The surface of the second dielectric layer and the via hole are treated with Lewis acid. Subsequently, the second photoresist layer is defined and formed on the second dielectric layer. Dry etching is proceed, and etching stop layer is as a etching terminal point to remove exposed partial surface of the second dielectric layer so as to form a trench having larger horizontal size than the via hole. Subsequently, the second photoresist layer is removed to form the opening of the damascene.

Abstract: A thermal flow photolithographic process. A thermal flow photoresist is provided. A cross-linking agent is added to the thermal flow photoresist to form a high-temperature cross-linking photoresist material. A substrate having an insulation layer thereon is provided. The high-temperature cross-linking photoresist is deposited over the insulation layer. The cross-linked photoresist layer on the insulation layer is exposed to light, chemically developed and then heated to cause thermal flow.

Abstract: A method is to form a dielectric layer with low dielectric constant on a hydrophilic dielectric layer. The method includes providing a substrate, which has a first dielectric layer on top. A hydrophilic second dielectric layer is formed on the first dielectric layer. A HMDS adhesion promoter layer is formed on the second dielectric layer. A dielectric layer with low dielectric constant, such as organic spin-on dielectric material or a hydrophilic dielectric material, is formed on the HMDS adhesion promoter layer. In the foregoing, the HMDS adhesion promoter layer has thickness of about 10-20 angstroms.

Abstract: A method of forming a multiple layer damascene structure. A substrate comprising of a multi-layered stack that includes, from bottom to top, a metallic layer, a first etching stop layer, a first dielectric layer, a second etching stop layer and a second dielectric layer is provided. A photoresist layer having large area openings and vias pattern is formed over the substrate. Large area openings and vias that expose a portion of the first etching stop layer are formed in the substrate. A barrier layer that fills all the large area openings and vias is formed over the substrate. Chemical-mechanical polishing is conducted to remove a portion of the barrier layer and expose the second dielectric layer. A second photoresist having a trench pattern thereon is formed over the substrate. Using the second photoresist as a mask, etching is conducted so that the second etching stop layer around the vias is exposed. Lastly, the barrier layer is removed.

Abstract: A barrier layer is formed over the substrate by deposition, and a first dielectric is formed over the diffusion barrier layer by deposition. A etching stop layer and a second dielectric are formed in turn over the first dielectric by deposition. Next, a hard mask is formed on the second dielectric. Then, a photoresist layer is formed over the hard mask, and defining the photoresist layer. And then dry etching is carried out by means of the photoresist layer as the mask to form a via hole. A gap-filling material is filled on the second dielectric and into the via hole by conventional partial-cured (or un-cured) spin-on glass method. A anti-reflection layer is formed over the second dielectric by deposition. Another photoresist layer is formed on the anti-reflection coating and defined the photoresist layer, and to expose the partial surface of the via hole and the anti-reflection coating.

Abstract: A three-phase phase shift mask. On a transparent substrate, a non-transparent pattern covering a portion of the transparent substrate is formed, while the other portion of the substrate is remained exposed. A proximity region around a comer of the non-transparent pattern is equally partitioned three phase-shift areas different from each other with a phase shift of 120°. The formation of these three phase-shift areas uses two etching steps to form a first and a second phase-shift areas, while a portion of the exposed substrate is etched twice as a third phase-shift area.

Abstract: An optical proximity correction method for rectifying pattern on negative photoresist. Line pattern of integrated circuit is divided into L-shape regions or T-shaped regions. The L-shaped or T-shaped regions are further dissected into rectangular patches. Area of each rectangular patch is suitably reduced and reproduced onto a photomask. The photomask is used to form a corrected photoresist pattern.