Abstract: A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of clock input pins can be connected with at least two asynchronous clock domains of the synchronization circuit in order to measure a timing signal between the flip-flop latches crossing the asynchronous clock domain. A timing delay with respect to each bit pair of the asynchronous clock domain can be determined utilizing a static analysis approach during a layout phase in order to effectively synchronize the asynchronous clock domain. Each bit pair of the asynchronous clock domain can be checked via a static timing analysis tool in order to thereby improve functional accuracy of the synchronization circuit in a wide range of digital logic designs.

Abstract: A method and system for eliminating implementation timing with respect to a synchronization circuit. A standard library cell having a pair of dock input pins can be connected with at least two asynchronous dock domains of the synchronization circuit in order to measure a timing signal between the flip-flop latches crossing the asynchronous clock domain. A timing delay with respect to each bit pair of the asynchronous dock domain can be determined utilizing a static analysis approach during a layout phase in order to effectively synchronize the asynchronous dock domain. Each bit pair of the asynchronous dock domain can be checked via a static timing analysis tool in order to thereby improve functional accuracy of the synchronization circuit in a wide range of digital logic designs.

Abstract: A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.

Abstract: A method and a computer program for configuring an integrated circuit design for static timing analysis include receiving module data representative of a hierarchy of modules in an integrated circuit design. A configuration item is selected from a list of configuration items for at least one of the modules. The module data is configured for the module from the selected configuration item into a static timing analysis scenario for performing a static timing analysis of the configured module data.