Patents by Inventor Ansgar Pottbaecker

Ansgar Pottbaecker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977508
    Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.
    Type: Grant
    Filed: March 24, 2022
    Date of Patent: May 7, 2024
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Jens Barrenscheen, Ansgar Pottbaecker
  • Publication number: 20220327092
    Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.
    Type: Application
    Filed: March 24, 2022
    Publication date: October 13, 2022
    Inventors: Jens Barrenscheen, Ansgar Pottbaecker
  • Patent number: 10216678
    Abstract: In one example, a master device connected in a serial-peripheral interface (SPI) daisy chain configuration with a plurality of servant devices, wherein the master device is configured to output a master data output to a first servant data input of a first servant device of a plurality of servant devices, wherein the plurality of servant devices are connected in a serial-peripheral interface (SPI) daisy chain configuration with the master device. The master device further configured to receive a master data input from a last servant device of the plurality of servant devices, wherein the master data input comprises an in-frame response of the plurality of servant devices, and wherein the in-frame response is received by the master device in a single SPI communication frame.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Diana Raluca Murtaza, Ansgar Pottbaecker
  • Patent number: 10193449
    Abstract: A buck voltage converter is provided which is configured so that a dominant pole of an open loop transfer function of the buck voltage converter is a pole introduced by a network comprising an inductor and a capacitor coupled to an output of the buck voltage converter.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: January 29, 2019
    Assignee: Infineon Technologies AG
    Inventors: Florin Biziitu, Ansgar Pottbaecker
  • Publication number: 20180375434
    Abstract: A buck voltage converter is provided which is configured so that a dominant pole of an open loop transfer function of the buck voltage converter is a pole introduced by a network comprising an inductor and a capacitor coupled to an output of the buck voltage converter.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Inventors: Florin Biziitu, Ansgar Pottbaecker
  • Patent number: 9923500
    Abstract: Techniques are described for providing, in a gate driver circuit, a compensation current to compensate for parasitic displacement current induced during the rising edge of an output voltage at an output gate of the gate driver circuit. In one example, the techniques of the disclosure include activating, by a bridge driver circuit for a direct-current (DC) motor, a driver of the bridge driver circuit and measuring, by the bridge driver circuit, a parasitic current of the driver during a rise time of an output gate voltage of the driver. In response to the measured parasitic current, generating, by the bridge driver circuit, a compensation current; and outputting, by the bridge driver circuit and to the output gate of the of the driver, the compensation current.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 20, 2018
    Assignee: Infineon Technologies AG
    Inventors: Detlef Ummelmann, Ansgar Pottbaecker
  • Publication number: 20180076747
    Abstract: Techniques are described for providing, in a gate driver circuit, a compensation current to compensate for parasitic displacement current induced during the rising edge of an output voltage at an output gate of the gate driver circuit. In one example, the techniques of the disclosure include activating, by a bridge driver circuit for a direct-current (DC) motor, a driver of the bridge driver circuit and measuring, by the bridge driver circuit, a parasitic current of the driver during a rise time of an output gate voltage of the driver. In response to the measured parasitic current, generating, by the bridge driver circuit, a compensation current; and outputting, by the bridge driver circuit and to the output gate of the of the driver, the compensation current.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Inventors: Detlef Ummelmann, Ansgar Pottbaecker
  • Patent number: 9672181
    Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Ansgar Pottbaecker, Fabrizio Cortigiani
  • Patent number: 9568933
    Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: February 14, 2017
    Assignees: STMicroelectronics R&D (Shanghai) Co. Ltd., STMicroelectronics Application GmbH
    Inventors: Ansgar Pottbaecker, Panny Cai
  • Patent number: 9405309
    Abstract: In one example, a method includes operating an LDO regulator system in one of a voltage regulation mode or a power balancing mode. The method further includes comparing one or more respective reference voltages to one or more respective feedback voltages to determine a change in amount of current that needs to be delivered by the LDO regulator system, wherein a first reference voltage is across a reference resistor and a first feedback voltage is across a shunt resistor, and in response to the change in the amount of current that needs to be delivered by the LDO regulator system, adjusting an amount of current flowing through a transistor to maintain a load at a constant output voltage level. Circuits and systems that implement the method are also described.
    Type: Grant
    Filed: November 29, 2014
    Date of Patent: August 2, 2016
    Assignee: Infineon Technologies AG
    Inventors: Florin Bîzîitu, Ansgar Pottbaecker, Paul David Patriche
  • Publication number: 20160154415
    Abstract: In one example, a method includes operating an LDO regulator system in one of a voltage regulation mode or a power balancing mode. The method further includes comparing one or more respective reference voltages to one or more respective feedback voltages to determine a change in amount of current that needs to be delivered by the LDO regulator system, wherein a first reference voltage is across a reference resistor and a first feedback voltage is across a shunt resistor, and in response to the change in the amount of current that needs to be delivered by the LDO regulator system, adjusting an amount of current flowing through a transistor to maintain a load at a constant output voltage level. Circuits and systems that implement the method are also described.
    Type: Application
    Filed: November 29, 2014
    Publication date: June 2, 2016
    Inventors: Florin Bîzîitu, Ansgar Pottbaecker, Paul David Patriche
  • Publication number: 20160098371
    Abstract: In one example, a master device connected in a serial-peripheral interface (SPI) daisy chain configuration with a plurality of servant devices, wherein the master device is configured to output a master data output to a first servant data input of a first servant device of a plurality of servant devices, wherein the plurality of servant devices are connected in a serial-peripheral interface (SPI) daisy chain configuration with the master device. The master device further configured to receive a master data input from a last servant device of the plurality of servant devices, wherein the master data input comprises an in-frame response of the plurality of servant devices, and wherein the in-frame response is received by the master device in a single SPI communication frame.
    Type: Application
    Filed: November 3, 2014
    Publication date: April 7, 2016
    Inventors: Diana Raluca Murtaza, Ansgar Pottbaecker
  • Patent number: 9281746
    Abstract: According to an embodiment, a diagnostic circuit is configured to be coupled to an output terminal of a switching circuit and to a sense terminal of a sense circuit coupled in parallel with the switching circuit. The diagnostic circuit includes a configurable feedback circuit configured to be coupled to the output terminal and the sense terminal. The configurable feedback circuit is configured to receive a select signal, switch a configuration of the configurable feedback circuit between a first mode and a second mode based on the select signal, sink a current from the sense circuit in the first mode, source a current to the sense circuit in the second mode, and balance a voltage difference between the output terminal and the sense terminal in the first mode and in the second mode.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 8, 2016
    Assignee: Infineon Technologies AG
    Inventors: Mihai-Nicolae Apostolescu, Ansgar Pottbaecker
  • Patent number: 9231520
    Abstract: An oscillator circuit includes a Wien-bridge oscillator. A non-detuned oscillating signal and a detuned oscillating signal are tapped from the Wien-bridge oscillator. A sum of a weighted detuned signal and a weighted non-detuned signal is coupled as feedback signal to the Wien-bridge to control the oscillation amplitude.
    Type: Grant
    Filed: March 21, 2013
    Date of Patent: January 5, 2016
    Assignee: Infineon Technologies AG
    Inventors: Detlef Ummelmann, Ansgar Pottbaecker
  • Publication number: 20150309950
    Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.
    Type: Application
    Filed: July 8, 2015
    Publication date: October 29, 2015
    Inventors: Jens Barrenscheen, Ansgar Pottbaecker, Fabrizio Cortigiani
  • Patent number: 9160559
    Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: October 13, 2015
    Assignee: Infineon Technologies, AG
    Inventors: Jens Barrenscheen, Ansgar Pottbaecker, Fabrizio Cortigiani
  • Publication number: 20140285274
    Abstract: An oscillator circuit includes a Wien-bridge oscillator. A non-detuned oscillating signal and a detuned oscillating signal are tapped from the Wien-bridge oscillator. A sum of a weighted detuned signal and a weighted non-detuned signal is coupled as feedback signal to the Wien-bridge to control the oscillation amplitude.
    Type: Application
    Filed: March 21, 2013
    Publication date: September 25, 2014
    Applicant: Infineon Technologies AG
    Inventors: Detlef Ummelmann, Ansgar Pottbaecker
  • Publication number: 20140070788
    Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.
    Type: Application
    Filed: September 9, 2013
    Publication date: March 13, 2014
    Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.
    Inventors: Ansgar Pottbaecker, Panny Cai
  • Publication number: 20130311691
    Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: Infineon Technologies AG
    Inventors: Jens Barrenscheen, Ansgar Pottbaecker, Fabrizio Cortigiani