Abstract: A DC/DC converter includes a converter stage to receive an input voltage and to provide an output voltage from the input voltage in accordance with a modulated drive signal. The converter stage further provides a feedback voltage representing the output voltage. A controller circuit includes an error amplifier to receive the feedback voltage and a reference voltage and to provide an error signal based on the feedback voltage and the reference voltage. A PWM modulator receives a clock signal and the error signal and generates a modulated signal based on the clock signal and the error signal, and a logic circuit receives the modulated signal and generates the drive signal for the converter stage based on the modulated signal so that the drive signal has the same duty cycle as the modulated signal, when the duty cycle of the modulated signal is not smaller than a minimum duty cycle value.

Abstract: A method for a slave bus and a master bus includes receiving a first frame via a first data channel, wherein the first frame includes at least first header data, first payload data and first checksum. The method further includes implementing a function depending on the header data contained in the received first frame, and generating a second frame including second header data, second payload data, which are determined by the implemented function, and a second checksum. The second checksum is ascertained at least on the basis of the second payload data and the first header data contained in the received first frame. The method also includes transmitting the second frame via a second data channel simultaneously with receiving the first frame via the first data channel.

Abstract: This disclosure includes systems, methods, and techniques for controlling delivery of power to a load. For example, a circuit includes a first switching device and a second switching device. The circuit is configured to activate, in response to a source voltage of a semiconductor device being lower than a first voltage, the first switching device in order to cause the circuit to deliver a first electrical signal to the semiconductor device, where the first electrical signal includes the first voltage and deactivate the first switching device in response to the source voltage of the semiconductor device not being lower than the first voltage. Additionally, the circuit is configured to activate, in response to the source voltage of the semiconductor device not being lower than the first voltage, the second switching device to cause the circuit to deliver a second electrical signal to the semiconductor device.

Abstract: In one example, a master device connected in a serial-peripheral interface (SPI) daisy chain configuration with a plurality of servant devices, wherein the master device is configured to output a master data output to a first servant data input of a first servant device of a plurality of servant devices, wherein the plurality of servant devices are connected in a serial-peripheral interface (SPI) daisy chain configuration with the master device. The master device further configured to receive a master data input from a last servant device of the plurality of servant devices, wherein the master data input comprises an in-frame response of the plurality of servant devices, and wherein the in-frame response is received by the master device in a single SPI communication frame.

Abstract: A buck voltage converter is provided which is configured so that a dominant pole of an open loop transfer function of the buck voltage converter is a pole introduced by a network comprising an inductor and a capacitor coupled to an output of the buck voltage converter.

Abstract: A buck voltage converter is provided which is configured so that a dominant pole of an open loop transfer function of the buck voltage converter is a pole introduced by a network comprising an inductor and a capacitor coupled to an output of the buck voltage converter.

Abstract: Techniques are described for providing, in a gate driver circuit, a compensation current to compensate for parasitic displacement current induced during the rising edge of an output voltage at an output gate of the gate driver circuit. In one example, the techniques of the disclosure include activating, by a bridge driver circuit for a direct-current (DC) motor, a driver of the bridge driver circuit and measuring, by the bridge driver circuit, a parasitic current of the driver during a rise time of an output gate voltage of the driver. In response to the measured parasitic current, generating, by the bridge driver circuit, a compensation current; and outputting, by the bridge driver circuit and to the output gate of the of the driver, the compensation current.

Abstract: Techniques are described for providing, in a gate driver circuit, a compensation current to compensate for parasitic displacement current induced during the rising edge of an output voltage at an output gate of the gate driver circuit. In one example, the techniques of the disclosure include activating, by a bridge driver circuit for a direct-current (DC) motor, a driver of the bridge driver circuit and measuring, by the bridge driver circuit, a parasitic current of the driver during a rise time of an output gate voltage of the driver. In response to the measured parasitic current, generating, by the bridge driver circuit, a compensation current; and outputting, by the bridge driver circuit and to the output gate of the of the driver, the compensation current.

Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.

Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

Abstract: In one example, a method includes operating an LDO regulator system in one of a voltage regulation mode or a power balancing mode. The method further includes comparing one or more respective reference voltages to one or more respective feedback voltages to determine a change in amount of current that needs to be delivered by the LDO regulator system, wherein a first reference voltage is across a reference resistor and a first feedback voltage is across a shunt resistor, and in response to the change in the amount of current that needs to be delivered by the LDO regulator system, adjusting an amount of current flowing through a transistor to maintain a load at a constant output voltage level. Circuits and systems that implement the method are also described.

Abstract: In one example, a method includes operating an LDO regulator system in one of a voltage regulation mode or a power balancing mode. The method further includes comparing one or more respective reference voltages to one or more respective feedback voltages to determine a change in amount of current that needs to be delivered by the LDO regulator system, wherein a first reference voltage is across a reference resistor and a first feedback voltage is across a shunt resistor, and in response to the change in the amount of current that needs to be delivered by the LDO regulator system, adjusting an amount of current flowing through a transistor to maintain a load at a constant output voltage level. Circuits and systems that implement the method are also described.

Abstract: In one example, a master device connected in a serial-peripheral interface (SPI) daisy chain configuration with a plurality of servant devices, wherein the master device is configured to output a master data output to a first servant data input of a first servant device of a plurality of servant devices, wherein the plurality of servant devices are connected in a serial-peripheral interface (SPI) daisy chain configuration with the master device. The master device further configured to receive a master data input from a last servant device of the plurality of servant devices, wherein the master data input comprises an in-frame response of the plurality of servant devices, and wherein the in-frame response is received by the master device in a single SPI communication frame.

Abstract: According to an embodiment, a diagnostic circuit is configured to be coupled to an output terminal of a switching circuit and to a sense terminal of a sense circuit coupled in parallel with the switching circuit. The diagnostic circuit includes a configurable feedback circuit configured to be coupled to the output terminal and the sense terminal. The configurable feedback circuit is configured to receive a select signal, switch a configuration of the configurable feedback circuit between a first mode and a second mode based on the select signal, sink a current from the sense circuit in the first mode, source a current to the sense circuit in the second mode, and balance a voltage difference between the output terminal and the sense terminal in the first mode and in the second mode.

Abstract: An oscillator circuit includes a Wien-bridge oscillator. A non-detuned oscillating signal and a detuned oscillating signal are tapped from the Wien-bridge oscillator. A sum of a weighted detuned signal and a weighted non-detuned signal is coupled as feedback signal to the Wien-bridge to control the oscillation amplitude.

Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.

Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.

Abstract: An oscillator circuit includes a Wien-bridge oscillator. A non-detuned oscillating signal and a detuned oscillating signal are tapped from the Wien-bridge oscillator. A sum of a weighted detuned signal and a weighted non-detuned signal is coupled as feedback signal to the Wien-bridge to control the oscillation amplitude.

Abstract: A bandgap reference voltage generator includes a bipolar assembly having a first resistor, a first branch and a second branch that is in parallel with the first branch. The first branch includes a first bipolar transistor with a base coupled to a fixed voltage. The second branch includes a second bipolar transistor with a base coupled to the fixed voltage and a second resistor coupled in series with the second bipolar transistor. A differential module is coupled to the first and second bipolar transistors and configured to balance the currents in the first and the second branches. The bandgap reference voltage is output at a node to which the first resistor is connected.

Abstract: A system includes a bus system, such as a LIN bus system. A number of components are connected to the bus system. A first component of the components is configured to detect a direction of a current to detect a location of the first component in the bus system. Each of the components can have a unique address.