Abstract: A method of designing a low power circuit that implements specified functionality, the method including: analyzing code for an algorithmic description of the specified functionality to generate a design representation of the circuit at the algorithmic level; instrumenting the code for the algorithmic description so as to capture data streams during execution/simulation of the algorithmic description; executing/simulating the instrumented code to generate an activity profile for the algorithmic description, wherein said activity profile includes at least portions of data traces of at least a portion of the executed algorithmic description; using the design representation to generate an initial hardware design that is an estimate of hardware resources necessary to implement at least some of the specified functionality; and computing power consumption for the initial hardware design based on the activity profile and power models for the hardware resources.

Abstract: The invention relates to a process and a corresponding device for circuit design by means of high-level synthesis in which a register-transfer description is determined from a system description of a circuit to be designed with an aim of designing the circuit with as little power consumption as possible. Particularly, in order to sufficiently take into account the more and more sharply increasing percentage of power consumption due to connecting wires, an iterative process is proposed in which, immediately after modification of an initial register-transfer description, a modified floorplan is also developed in which it can be recognized immediately whether or not the modification of the initial register-transfer description has brought with it a reduction of the power consumption of the connecting wires.

Abstract: A method of designing a low power circuit that implements specified functionality, the method including: analyzing code for an algorithmic description of the specified functionality to generate a design representation of the circuit at the algorithmic level; instrumenting the code for the algorithmic description so as to capture data streams during execution/simulation of the algorithmic description; executing/simulating the instrumented code to generate an activity profile for the algorithmic description, wherein said activity profile includes at least portions of data traces of at least a portion of the executed algorithmic description; using the design representation to generate an initial hardware design that is an estimate of hardware resources necessary to implement at least some of the specified functionality; and computing power consumption for the initial hardware design based on the activity profile and power models for the hardware resources.

Abstract: The invention relates to a process and a corresponding device for circuit design by means of high-level synthesis in which a register-transfer description is determined from a system description of the circuit to be designed with the aim of designing a circuit with as little power consumption as possible. Particularly, in order to sufficiently take into account the more and more sharply increasing percentage of the power consumption due to the connecting wires, an iterative process is proposed in which, immediately after modification of the initial register-transfer description, a modified floorplan is also developed in which it can be recognized immediately whether or not the modification of the register-transfer description has brought with it a reduction of the power consumption of the connecting wires.