Patents by Inventor Ansgar Teipel

Ansgar Teipel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7251016
    Abstract: A method for correcting structure-size-dependent positioning errors during the photolithographic projection by an exposure apparatus and the use thereof includes providing an exposure apparatus for exposing a plurality of exposure fields and a simulation model of the exposure apparatus for specifying correction values for intra-field errors, providing a first pattern with first structure elements and first measurement marks, which, in the case of a projection, are beset by a first positioning error and a second positioning error dependent on the dimensions and the position in the exposure field, providing a correction function suitable for specifying the first and the second positioning error, determining an average relative positioning error including the first and the second positioning error, calculating correction values for the control of the exposure apparatus, and transmitting the correction values to the exposure apparatus so that subsequent exposures are performed with an improved overlay.
    Type: Grant
    Filed: July 27, 2005
    Date of Patent: July 31, 2007
    Assignee: Infineon Technologies AG
    Inventors: Hans-Georg Froehlich, Manuel Vorwerk, Ansgar Teipel
  • Patent number: 7084962
    Abstract: A method, suitable to photolithographie projection, for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure into at least one resist layer above the substrate, wherein the first test structure includes a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 1, 2006
    Assignee: Infineon Technologies AG
    Inventors: Lothar Bauch, Stefan Gruss, Ansgar Teipel, Hans-Georg Froehlich
  • Publication number: 20060023198
    Abstract: A method for correcting structure-size-dependent positioning errors during the photolithographic projection by an exposure apparatus and the use thereof includes providing an exposure apparatus for exposing a plurality of exposure fields and a simulation model of the exposure apparatus for specifying correction values for intra-field errors, providing a first pattern with first structure elements and first measurement marks, which, in the case of a projection, are beset by a first positioning error and a second positioning error dependent on the dimensions and the position in the exposure field, providing a correction function suitable for specifying the first and the second positioning error, determining an average relative positioning error including the first and the second positioning error, calculating correction values for the control of the exposure apparatus, and transmitting the correction values to the exposure apparatus so that subsequent exposures are performed with an improved overlay.
    Type: Application
    Filed: July 27, 2005
    Publication date: February 2, 2006
    Inventors: Hans-Georg Froehlich, Manuel Vorwerk, Ansgar Teipel
  • Publication number: 20050068515
    Abstract: The invention relates to a method for detecting the positioning errors of circuit patterns during the transfer by a mask into layers of a substrate of a semiconductor wafer. After the transfer of at least one multiple arrangement of a first test structure by means of photolithographic projection into at least one resist layer above the substrate, the first test structure having a first circuit pattern, at least one first overlay mark and at least one first micropatterned alignment mark, the values of a first positioning error of the first circuit patterns relative to the first overlay marks and the first micropatterned alignment marks are determined for each element of the at least one multiple arrangement.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 31, 2005
    Inventors: Lothar Bauch, Stefan Gruss, Ansgar Teipel, Hans-Georg Froehlich