Abstract: This disclosure is directed to performing a controlled reset of one or more cores while maintaining operation of at least one other core in a multi-core processor. An initialization core may include reset logic that may detect a problematic core or core that is unresponsive or otherwise not operating properly. The initialization core may generate a packet that enables communication with the problematic core. The initialization core may send a reset packet to the problematic core to instruct the problematic core to perform a reset.

Abstract: An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.