Patents by Inventor Anshuman Verma

Anshuman Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260197376
    Abstract: Examples solutions for evaluating network connectivity between computing resources within a computing environment include: generating a network packet for a proxy ping at a first host server that provides a first virtual machine (VM), the network packet being originally generated by the first host server and not generated by the first VM, the network packet being created to include a proxy ping flag within a header of the network packet; capturing a sending timestamp; receiving a response network packet generated by a second host server in response to interception of the network packet without the network packet being sent through to the second VM, the network packet having been identified for interception by the second host server based on identifying the proxy ping flag within the header of the network packet; capturing a response timestamp; and computing a latency value based on a difference between the sending and response timestamps.
    Type: Application
    Filed: February 18, 2025
    Publication date: July 9, 2026
    Inventors: Vincent Vu Phan NGUYEN, Harish SRINIVASAN, Milan DASGUPTA, Anshuman VERMA
  • Publication number: 20260197375
    Abstract: Examples solutions for evaluating network connectivity between computing resources within a computing environment include: generating a network packet for a proxy ping at a first host server that provides a first virtual machine (VM), the network packet being originally generated by the first host server and not generated by the first VM, the network packet being created to include a proxy ping flag within a header of the network packet; capturing a sending timestamp; receiving a response network packet generated by a second host server in response to interception of the network packet without the network packet being sent through to the second VM, the network packet having been identified for interception by the second host server based on identifying the proxy ping flag within the header of the network packet; capturing a response timestamp; and computing a latency value based on a difference between the sending and response timestamps.
    Type: Application
    Filed: January 9, 2025
    Publication date: July 9, 2026
    Inventors: Vincent Vu Phan NGUYEN, Harish SRINIVASAN, Milan DASGUPTA, Anshuman VERMA
  • Patent number: 12652257
    Abstract: A computerized method for processing packets in parallel using a reorder queue is described. As packets are received, it is determined which packet is the first packet in the flow. Once identified, the first packet in the flow, along with all other packets in the flow, is sent to the reorder queue while only a copy of the first packet in the flow is sent to a packet scheduler for processing on one of a plurality of processing cores. After the copy of the first packet in the flow is processed, the reorder queue releases each of the packets for the flow from the reorder queue in an order in which they were received. Thereafter, each of the packets released from the reorder queue are processed based on the processing of the copy of the first packet.
    Type: Grant
    Filed: June 19, 2023
    Date of Patent: June 9, 2026
    Assignee: Microsoft Technology Licensing, LLC.
    Inventors: Tian Tan, Anshuman Verma, Tushar Garg, Taylor Catherine Swanson
  • Publication number: 20260140761
    Abstract: A hardware device is communicatively connected to host servers individually supporting a virtual switch and one or more virtual machines and includes a processor input to receive a header of a data packet in the hardware device, a hardware rules processor scheduler to schedule processing of the header among hardware processing cores in the hardware rules processor, a rules processor core scheduled by the hardware rules processor scheduler to receive the header from the hardware rules processor scheduler, the rules processor core to read compiled networking policies from the memory, and to apply the compiled networking policies to the header to yield a modified header for the data packet, and a connection establishment processor to record the networking connection for the data packet based on the modified header in an established connection datastore.
    Type: Application
    Filed: November 15, 2024
    Publication date: May 21, 2026
    Inventors: Tian TAN, Vivek BHANU, Osman Nuri ERTUGAY, Harish SRINIVASAN, Daniel Max FIRESTONE, Alireza DABAGH, Zachary Noel LIBBY, Narayanan RAVICHANDRAN, Derek Tsungkai CHIOU, Ahmed ABDELSALAM, Tushar GARG, Taylor Catherine SWANSON, Milan DASGUPTA, Nadeen Yassir GEBARA, Georgia Olivia WALKER, Anshuman VERMA
  • Patent number: 12625808
    Abstract: The present disclosure relates to a cache memory and methods that handle data forwarding from the cache memory to an action block to perform an action on the data. The action block performs an action on the data and outputs modified data in response to performing the action. The cache memory and methods use a latency parameter for data forwarding to prevent data hazards from occurring and to meet timing requirements and performance requirements of the cache memory.
    Type: Grant
    Filed: February 14, 2023
    Date of Patent: May 12, 2026
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ahmed Abdelsalam, Vishalkumar Shantilal Gondaliya, Anshuman Verma, Robert Groza, Jr., Dongwook Lee, Ezzeldin Hamed
  • Publication number: 20260067217
    Abstract: A method of forcefully terminating a flow includes identifying, by a hardware accelerator, a flow entry in a flow table corresponding to a flow determined to satisfy predefined criteria for flow termination and transmitting, by the hardware accelerator, a flow termination request to a software-based reset packet generator. The flow termination request includes flow match characteristics included in the flow entry of the flow table. The method further includes generating, at the software-based reset packet generator, a first transport control protocol (TCP) reset packet with header information matching the flow match characteristics and transmitting the first TCP reset packet to the hardware accelerator. The method still further provides for transforming the first TCP reset packet, at the hardware accelerator, according to a first transformation defined in the flow entry. The transformed TCP reset packet is transmitted to the destination device and the flow entry is deleted from the flow table.
    Type: Application
    Filed: August 30, 2024
    Publication date: March 5, 2026
    Inventors: Ahmed ABDELSALAM, Osman Nuri ERTUGAY, Zachary Noel LIBBY, Narayanan RAVICHANDRAN, Rohan KANDI, Milan DASGUPTA, Anshuman VERMA, Lok Chand KOPPAKA, Harish SRINIVASAN
  • Publication number: 20250267006
    Abstract: According to examples, a hardware component for acceleration of QUIC data packets includes a data store on which is stored a first table and a second table, in which the first table and the second table respectively store information corresponding to a direction in which the QUIC data packets are to flow through a network. The hardware component includes a plurality of logic elements that are to receive information for a QUIC connection, determine a direction of initiation of the QUIC connection, and cause the received information to be stored in one of the first table and the second table depending upon the determined direction of the QUIC connection initiation.
    Type: Application
    Filed: February 17, 2024
    Publication date: August 21, 2025
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Pragati Medleri HIRE MATH, Ahmed ABDELSALAM, Raymond LIU, Abhipsa UJWAL, Daniel LY-MA, Alexander MALYSH, Anshuman VERMA, Dongwook LEE, Harish SRINIVASAN
  • Publication number: 20240422106
    Abstract: A computerized method for processing packets in parallel using a reorder queue is described. As packets are received, it is determined which packet is the first packet in the flow. Once identified, the first packet in the flow, along with all other packets in the flow, is sent to the reorder queue while only a copy of the first packet in the flow is sent to a packet scheduler for processing on one of a plurality of processing cores. After the copy of the first packet in the flow is processed, the reorder queue releases each of the packets for the flow from the reorder queue in an order in which they were received. Thereafter, each of the packets released from the reorder queue are processed based on the processing of the copy of the first packet.
    Type: Application
    Filed: June 19, 2023
    Publication date: December 19, 2024
    Inventors: Tian TAN, Anshuman VERMA, Tushar GARG, Taylor Catherine SWANSON
  • Publication number: 20240273021
    Abstract: The present disclosure relates to a cache memory and methods that handle data forwarding from the cache memory to an action block to perform an action on the data. The action block performs an action on the data and outputs modified data in response to performing the action. The cache memory and methods use a latency parameter for data forwarding to prevent data hazards from occurring and to meet timing requirements and performance requirements of the cache memory.
    Type: Application
    Filed: February 14, 2023
    Publication date: August 15, 2024
    Inventors: Ahmed ABDELSALAM, Vishalkumar Shantilal GONDALIYA, Anshuman VERMA, Robert GROZA, JR., Dongwook LEE, Ezzeldin HAMED
  • Publication number: 20190058120
    Abstract: A vertical interconnect via having a first array of first metal interconnect wires extending along a first lateral direction made from a first material and a second array of second interconnect wires extending along a second lateral direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a metal-insulator-metal structure. The said metal-insulator-metal structure transforms to metal-metal-metal structure upon an application of electric pulse.
    Type: Application
    Filed: October 23, 2018
    Publication date: February 21, 2019
    Inventors: Marius Orlowski, Gargi Ghosh, Anshuman Verma
  • Publication number: 20170155045
    Abstract: A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.
    Type: Application
    Filed: November 30, 2016
    Publication date: June 1, 2017
    Inventors: Marius Orlowski, Gargi Ghosh, Anshuman Verma