Abstract: A computerized method for processing packets in parallel using a reorder queue is described. As packets are received, it is determined which packet is the first packet in the flow. Once identified, the first packet in the flow, along with all other packets in the flow, is sent to the reorder queue while only a copy of the first packet in the flow is sent to a packet scheduler for processing on one of a plurality of processing cores. After the copy of the first packet in the flow is processed, the reorder queue releases each of the packets for the flow from the reorder queue in an order in which they were received. Thereafter, each of the packets released from the reorder queue are processed based on the processing of the copy of the first packet.

Abstract: The present disclosure relates to a cache memory and methods that handle data forwarding from the cache memory to an action block to perform an action on the data. The action block performs an action on the data and outputs modified data in response to performing the action. The cache memory and methods use a latency parameter for data forwarding to prevent data hazards from occurring and to meet timing requirements and performance requirements of the cache memory.

Abstract: A vertical interconnect via having a first array of first metal interconnect wires extending along a first lateral direction made from a first material and a second array of second interconnect wires extending along a second lateral direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a metal-insulator-metal structure. The said metal-insulator-metal structure transforms to metal-metal-metal structure upon an application of electric pulse.

Abstract: A memory device having a first array of first electrodes extending along a first direction made from a first material and a second array of second electrodes extending along a second direction made from a second material. An intersection defined by the first array and the second array, wherein each intersection of the first array and the second array defines a two-terminal resistive memory cell, said memory cell formed by a conductive path between said first and second electrodes.