Patents by Inventor Anson J. Call
Anson J. Call has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10956649Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: GrantFiled: August 22, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Patent number: 10770385Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.Type: GrantFiled: July 26, 2018Date of Patent: September 8, 2020Assignee: International Business Machines CorporationInventors: Anson J. Call, Brian W. Quinlan, Krishna R. Tunga
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Patent number: 10607928Abstract: An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.Type: GrantFiled: August 1, 2019Date of Patent: March 31, 2020Assignee: International Business Machines CorporationInventors: Anson J. Call, Sushumna Iruvanti, Shidong Li, Brian W. Quinlan, Kamal K. Sikka, Rui Wang
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Publication number: 20200035593Abstract: An integrated circuit (IC) chip carrier includes an internal connected plane stiffener. The connected plane stiffener includes a first plane connected to a second plane by a channel via. The first plane is separated from the second plane a plane separation dielectric layer. The channel via is within the plane separation dielectric layer. The first plane and the second plane resist bending moments internal to the IC chip carrier. The channel via resists shear forces internal to the IC chip carrier. The first plane and the second plane may be both power planes that distributes power potential within the IC chip carrier. The first plane and the second plane may be both ground planes that distributes ground potential within the IC chip carrier.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: Anson J. Call, Brian W. Quinlan, Krishna R. Tunga
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Patent number: 10546096Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.Type: GrantFiled: September 29, 2017Date of Patent: January 28, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anson J. Call, Paul R. Walling
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Publication number: 20190377850Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: ApplicationFiled: August 22, 2019Publication date: December 12, 2019Inventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Patent number: 10483233Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.Type: GrantFiled: January 26, 2017Date of Patent: November 19, 2019Assignee: International Business Machines CorporationInventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
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Patent number: 10423752Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: GrantFiled: September 29, 2017Date of Patent: September 24, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Patent number: 10276534Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.Type: GrantFiled: August 8, 2017Date of Patent: April 30, 2019Assignee: International Business Machines CorporationInventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
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Patent number: 10276535Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.Type: GrantFiled: October 26, 2017Date of Patent: April 30, 2019Assignee: International Business Machines CorporationInventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
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Publication number: 20190102506Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Anson J. Call, Francesco Preda, Paul R. Walling
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Publication number: 20190102504Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.Type: ApplicationFiled: September 29, 2017Publication date: April 4, 2019Inventors: Anson J. Call, Paul R. Walling
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Patent number: 10108753Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.Type: GrantFiled: June 7, 2016Date of Patent: October 23, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
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Publication number: 20180061799Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.Type: ApplicationFiled: August 8, 2017Publication date: March 1, 2018Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
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Publication number: 20180061800Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.Type: ApplicationFiled: October 26, 2017Publication date: March 1, 2018Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
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Patent number: 9865557Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.Type: GrantFiled: August 30, 2016Date of Patent: January 9, 2018Assignee: International Business Machines CorporationInventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
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Publication number: 20170351783Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.Type: ApplicationFiled: June 7, 2016Publication date: December 7, 2017Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
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Publication number: 20170141078Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.Type: ApplicationFiled: January 26, 2017Publication date: May 18, 2017Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
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Patent number: 9633914Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.Type: GrantFiled: September 15, 2015Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
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Publication number: 20170077000Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble