Patents by Inventor Anson J. Call

Anson J. Call has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190377850
    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.
    Type: Application
    Filed: August 22, 2019
    Publication date: December 12, 2019
    Inventors: Anson J. Call, Francesco Preda, Paul R. Walling
  • Patent number: 10483233
    Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
  • Patent number: 10423752
    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anson J. Call, Francesco Preda, Paul R. Walling
  • Patent number: 10276534
    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 10276535
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: April 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20190102506
    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking metal coverage in a laminate structure. Aspects of the invention include receiving, by a processor, metal shadowing rules and a semiconductor package design comprising a plurality of laminate layers, a plurality of metal power shapes, and a plurality of signal lines. Each metal power shape is mapped to one or more cells in a two-dimensional array. The processor determines, for each signal line in the semiconductor package design, whether the metal power shapes satisfy the metal shadowing rules. The processor displays a list of signal lines that do not satisfy the metal shadowing rules.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Anson J. Call, Francesco Preda, Paul R. Walling
  • Publication number: 20190102504
    Abstract: Embodiments of the invention include methods, systems, and computer program products for checking semiconductor package via proximity rules. Aspects of the invention include receiving, by a processor, the via proximity rules and a semiconductor package design including one or more package layers and a plurality of vias. Each via is mapped to a cell in a three-dimensional array and a via stack including each via is identified. The via stacks are checked against the via proximity rules. A list of via stacks which did not satisfy the via proximity rules is displayed on a user interface.
    Type: Application
    Filed: September 29, 2017
    Publication date: April 4, 2019
    Inventors: Anson J. Call, Paul R. Walling
  • Patent number: 10108753
    Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20180061799
    Abstract: A first electrical contact and second contact is upon an interposer and/or upon a processing device. The first contact includes a minor axis and a major axis. The second contact includes diameter axes. The first contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The first electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The first electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring first electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring first electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Application
    Filed: August 8, 2017
    Publication date: March 1, 2018
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20180061800
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Application
    Filed: October 26, 2017
    Publication date: March 1, 2018
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 9865557
    Abstract: An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major axis is generally aligned with the direction of expansion of the interposer and/or the processing device. The electrical contact may further be positioned within a power/ground or input/output (I/O) region of the interposer and/or processing device. The electrical contact may further be positioned within a center region that is surrounded by a perimeter region of the interposer and/or the processing device. The dimensions or aspect ratios of major and minor axes of neighboring electrical contacts within an electrical contact grid may differ relative thereto. Further, the angle of respective major and minor axes of neighboring electrical contacts within the electrical contact grid may differ relative thereto.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: January 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20170351783
    Abstract: Method of designing a laminate substrate having upper laminate layers and an equal plurality of lower laminate layers including: dividing the laminate substrate into regions having corresponding laminate layer pairs consisting of an upper laminate layer and a lower laminate layer; calculating a net stretching value for each corresponding laminate layer pair in each region to result in net stretching values in each region; summing the net stretching values in each region to result in a net stretching value for each region proportional to a curvature of each local region; calculating a relative out-of-plane displacement for the laminate substrate from the curvature of each local region; calculating a predicted thermal warpage for the laminate substrate; and finalizing a design of the laminate substrate when the predicted thermal warpage is within a predetermined acceptable range.
    Type: Application
    Filed: June 7, 2016
    Publication date: December 7, 2017
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Publication number: 20170141078
    Abstract: A multi-chip module, and method of fabricating the multi-chip module. The multi-chip module includes: a substrate containing multiple wiring layers, each wiring layer having first pads on a top surface of the substrate and second pads on a bottom surface of the substrate, wherein the second pads include split pad and a conventional pad; a first solder ball in direct physical contact with a contiguous bottom surface of the conventional pad and connected to a next level of packaging under the conventional pad, wherein the first solder ball has a first height; and a second solder ball in direct physical contact with first and second sections of the split pad separated by a gap, wherein the second solder ball has a second height that is sufficiently less than the first height such that the second solder ball is not connected to the next level of packaging.
    Type: Application
    Filed: January 26, 2017
    Publication date: May 18, 2017
    Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
  • Patent number: 9633914
    Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
  • Publication number: 20170077000
    Abstract: A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads.
    Type: Application
    Filed: September 15, 2015
    Publication date: March 16, 2017
    Inventors: Anson J. Call, Erwin B. Cohen, Dany Minier, Wolfgang Sauter, David B. Stone, Eric W. Tremble
  • Patent number: 9563732
    Abstract: A method of predicting warpage of a laminate is disclosed in which in-plane copper imbalance is calculated. A method of designing an organic build-up laminate is provided in which in-plane copper imbalance is calculated and imbalances are corrected.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: February 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anson J. Call, Vijayeshwar D. Khanna, David J. Russell, Krishna R. Tunga
  • Patent number: 7786579
    Abstract: A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.
    Type: Grant
    Filed: May 23, 2007
    Date of Patent: August 31, 2010
    Assignee: International Business Machines Corporation
    Inventors: Jean Audet, Anson J. Call, Steven P. Ostrander, Douglas O. Powell, Roger D. Weekly
  • Publication number: 20080290510
    Abstract: A microelectronic package having integrated circuits is provided. The microelectronic package includes multiple dielectric laminate layers, copper circuitry between the dielectric laminate layers where the copper circuitry includes circuit traces, and ball grid arrays/land grid arrays operatively connected to the copper circuitry such that conduction occurs. Further, proximate to the connection of the copper circuitry and the ball grid arrays/land grid arrays, a protective copper tongue is below an extension of the circuit traces, such that the protective copper tongue prevents the circuit traces from being affected by cracking propagated in the dielectric laminate layers or the ball grid arrays/land grid arrays.
    Type: Application
    Filed: May 23, 2007
    Publication date: November 27, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jean Audet, Anson J. Call, Steven P. Ostrander, Douglas O. Powell, Roger D. Weekly
  • Publication number: 20080072597
    Abstract: A liquid piston engine utilizing an electronically or electrically conductive liquid medium. A method is provided for utilizing the electrically conductive liquid piston engine.
    Type: Application
    Filed: September 21, 2006
    Publication date: March 27, 2008
    Applicant: International Business Machines Corporation
    Inventor: Anson J. Call
  • Patent number: 6584684
    Abstract: A module or assembly is formed by interposing a polymer between a carrier and a semiconductor device to be secured to the carrier. The polymer has ionized metallic particles suspended in it. Before setting or curing the polymer, the module is exposed to an electric field which induces migration of the metallic particles to the opposing pads of the carrier and semiconductor device. Such migration ultimately forms metal dendrites extending between mating pad pairs. The dendrites establish a metallurgical bond and conductive paths between the carrier and the overlying semiconductor device. When the polymer is subsequently set, the carrier and device are not only adhered to each other, but the dendrite connections are fixed and structurally reinforced to provide the needed electrically conductive paths.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines
    Inventors: Peter J. Brofman, Anson J. Call, Jeffrey T. Coffin, Kathleen A. Stalter