Patents by Inventor Anson Jay Call

Anson Jay Call has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Copper feature design for warpage control of substrates
    Patent number: 9659131
    Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
  • Copper Feature Design for Warpage Control of Substrates
    Publication number: 20150317423
    Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.
    Type: Application
    Filed: June 29, 2015
    Publication date: November 5, 2015
    Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
  • Copper feature design for warpage control of substrates
    Patent number: 9105535
    Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer that includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
  • Copper Feature Design for Warpage Control of Substrates
    Publication number: 20130334711
    Abstract: An approach is provided in which a laminate substrate includes top layers, bottom layers, and a core layer. The top layers are positioned between the core layer and a top surface metallurgy (TSM) layer and include at least one top conductive layer. The bottom layers are positioned between the core layer and a bottom surface metallurgy (BSM) layer and include at least one bottom conductive layer includes a material void pattern that is based upon the top conductive layer and reduces warpage of the laminate substrate.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: International Business Machines Corporation
    Inventors: Edmund Blackshear, Anson Jay Call, Vijayeshwar Das Khanna, Douglas Oliver Powell, David John Russell
  • Aryl Cyanate and/or diepoxide and tetrahydropyranyl-protected hydroxymethylated phenolic or hydroxystyrene resin
    Patent number: 6114450
    Abstract: An adhesive for bonding a die of an integrated circuit chip comprises an aryl cyanate (ester) resin and/or a diepoxide resin admixed with tetrahydropyranyl-protected hydroxylmethylated phenolic resin or hydroxymethylated poly(hydroxystyrene) optionally further containing an electrically or thermally conductive filler.
    Type: Grant
    Filed: May 4, 1999
    Date of Patent: September 5, 2000
    Assignee: International Business Corporation
    Inventors: Krishna Gandhi Sachdev, Michael Berger, Anson Jay Call, Frank Louis Pompeo Jr.
  • Aryl cyanate and/or diepoxide and hydroxymethylated phenolic or hydroxystyrene resin
    Patent number: 5955543
    Abstract: An adhesive for bonding a die of an integrated circuit chip comprises an aryl cyanate (ester) resin alone and/or a diepoxide resin admixed with a hydroxymethylated phenolic resin or hydroxymethylated poly(hydroxystyrene) which can further contain an electrically or thermally conductive filler.
    Type: Grant
    Filed: May 21, 1997
    Date of Patent: September 21, 1999
    Assignee: International Business Machines Corporation
    Inventors: Krishna Gandhi Sachdev, Michael Berger, Anson Jay Call, Frank Louis Pompeo, Jr.
  • Reworkable polymer chip encapsulant
    Patent number: 5930597
    Abstract: A C4 or flip chip reworkable electronic device is provided comprising an integrated circuit chip having conductive pads thereon which pads are electrically connected to corresponding pads on an interconnection substrate by solder connections, wherein the space between the chip and substrate is sealed using a specially defined thermoplastic resin such as polysulfone and polyetherimide.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: Anson Jay Call, Stephen Leslie Buchwalter, Sushumna Iruvanti, Stanley J. Jasne, Frank L. Pompeo, Jr., Paul Anthony Zucco, Wayne Martin Moreau
  • Reworkable polymer chip encapsulant
    Patent number: 5659203
    Abstract: A C4 or flip chip reworkable electronic device is provided comprising integrated circuit chip having conductive pads thereon which pads are electrically connected to corresponding pads on an interconnection substrate by solder connections, wherein the space between the chip and substrate is sealed using a specially defined thermoplastic resin such as polysulfone and polyetherimide.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventors: Anson Jay Call, Stephen Leslie Buchwalter, Sushumna Iruvanti, Stanley J. Jasne, Frank L. Pompeo, Jr., Paul Anthony Zucco, Wayne Martin Moreau