Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.

Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.

Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.

Abstract: Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of each work unit of the workload and assigning a time slice to each work unit of the workload based on the cache/memory footprint of each work unit. Aspects further include executing the workload on a processor by providing each work unit access to the processor for the time slice assigned to each work unit.

Abstract: A technique for simultaneous multithreading (SMT) by a computer is provided. An operating system or a second-level hypervisor of the computer manages a logical core configuration for simultaneous multithreading. The operating system or the second-level hypervisor has control over a logical core and control over logical threads on the logical core. The operating system or the second-level hypervisor of the computer configures a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core. The logical core is run on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core.

Abstract: A technique for chargeback with simultaneous multithreading (SMT) by a computer is provided. One or more of an operating system and a second-level hypervisor of the computer manage a logical core configuration for simultaneous multithreading, the operating system and/or the second-level hypervisor has control over a logical core and control over logical threads on the logical core. The operating system and/or the second-level hypervisor is configures a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core. The logical core is run on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core. A capacity use time is determined for each of the logical threads executing on the physical threads of the single physical core.

Abstract: A technique for chargeback with simultaneous multithreading (SMT) by a computer is provided. One or more of an operating system and a second-level hypervisor of the computer manage a logical core configuration for simultaneous multithreading, the operating system and/or the second-level hypervisor has control over a logical core and control over logical threads on the logical core. The operating system and/or the second-level hypervisor is configures a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core. The logical core is run on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core. A capacity use time is determined for each of the logical threads executing on the physical threads of the single physical core.

Abstract: A technique for simultaneous multithreading (SMT) by a computer is provided. An operating system or a second-level hypervisor of the computer manages a logical core configuration for simultaneous multithreading. The operating system or the second-level hypervisor has control over a logical core and control over logical threads on the logical core. The operating system or the second-level hypervisor of the computer configures a host hypervisor to assign an entirety of the logical core to a single physical core, such that one logical core executes per physical core. The logical core is run on the single physical core on an exclusive basis for a period of time, such that the logical threads of the logical core execute on physical threads of the single physical core.