Patents by Inventor Antariksh Rao Pratap SINGH

Antariksh Rao Pratap SINGH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240258183
    Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.
    Type: Application
    Filed: April 10, 2024
    Publication date: August 1, 2024
    Inventors: Edvin CETEGEN, Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Nicholas NEAL, Sergio CHAN ARGUEDAS, Vipul MEHTA
  • Patent number: 12009271
    Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: June 11, 2024
    Assignee: Intel Corporation
    Inventors: Edvin Cetegen, Jacob Vehonsky, Nicholas S. Haehn, Thomas Heaton, Steve S. Cho, Rahul Jain, Tarek Ibrahim, Antariksh Rao Pratap Singh, Nicholas Neal, Sergio Chan Arguedas, Vipul Mehta
  • Publication number: 20230343723
    Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Nicholas NEAL, Nicholas S. HAEHN, Sergio CHAN ARGUEDAS, Edvin CETEGEN, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON
  • Patent number: 11776864
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Jacob Vehonsky, Nicholas S. Haehn, Thomas Heaton, Steve S. Cho, Rahul Jain, Tarek Ibrahim, Antariksh Rao Pratap Singh, Edvin Cetegen, Nicholas Neal, Sergio Chan Arguedas
  • Publication number: 20210066162
    Abstract: A device is disclosed. The device includes a substrate, a die on the substrate, a thermal interface material (TIM) on the die, and solder bumps on a periphery of a top surface of the substrate. An integrated heat spreader (IHS) is formed on the solder bumps. The IHS covers the TIM.
    Type: Application
    Filed: August 30, 2019
    Publication date: March 4, 2021
    Inventors: Sergio A. CHAN ARGUEDAS, Nicholas S. HAEHN, Edvin CETEGEN, Nicholas NEAL, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON, Vipul MEHTA
  • Publication number: 20210035921
    Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 4, 2021
    Inventors: Nicholas NEAL, Nicholas S. HAEHN, Sergio CHAN ARGUEDAS, Edvin CETEGEN, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON
  • Publication number: 20210020531
    Abstract: Embodiments disclosed herein include electronic packages with underfill flow control features. In an embodiment, an electronic package comprises a package substrate and a plurality of interconnects on the package substrate. In an embodiment, a die is coupled to the package substrate by the plurality of interconnects and a flow control feature is adjacent on the package substrate. In an embodiment, the flow control feature is electrically isolated from circuitry of the electronic package. In an embodiment, the electronic package further comprises an underfill surrounding the plurality of interconnects and in contact with the flow control feature.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Edvin CETEGEN, Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Nicholas NEAL, Sergio CHAN ARGUEDAS, Vipul MEHTA
  • Publication number: 20210020532
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.
    Type: Application
    Filed: July 15, 2019
    Publication date: January 21, 2021
    Inventors: Jacob VEHONSKY, Nicholas S. HAEHN, Thomas HEATON, Steve S. CHO, Rahul JAIN, Tarek IBRAHIM, Antariksh Rao Pratap SINGH, Edvin CETEGEN, Nicholas NEAL, Sergio CHAN ARGUEDAS