Abstract: The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and different operand data of the instructions to respective ones of the processing elements (10). Under control of the instructions each processing element (10) determines, whether an operand data dependent condition has occurred. The processing element outputs a condition signal dependent on said determination. The condition signals are summed to form a sum signal. Program flow is controlled by a conditional jump dependent on a value represented by the sum signal.

Abstract: A SIMD processor architecture (2) for processing a stream of data vectors is provided, the architecture comprising a processor array (4) comprising a plurality of processors (PE(0), . . . , (PE(N)), each processor ((PE(0), . . . PE(N)) being adapted to process a data element in each vector, the operation of the processor array (4) being controlled by a local clock signal having a first frequency; a control processor (16) adapted to control the operation of the SIMD processor architecture (2) and generate signals to synchronize the operation of the processor array (4) with the stream of data vectors, the operation of the control processor (16) being controlled by a local clock signal having a second frequency; and power management means (30) for adjusting the frequencies of the local clock signals in response to the synchronization signals generated by the control processor (16), thereby minimizing the power consumption of the SIMD processor architecture (2).

Abstract: A SIMD processor architecture comprises a Linear Processor Array (LPA) (41) having a plurality of Processing Elements (PEs) (42). Each PE (42) operates on its pixel data based on a common instruction which is broadcast to all PEs (42) from a global control processor (44). To enhance the processor's capability in handling de-interlacing algorithms, there is provided a field access module (FAM) (47), an input line memory (48), and a shadow memory (49) within a working line memory (43). The input line memory (48) comprises a previous video field memory (481) for storing a first plurality of pixels from a previous video field, a current video field memory (482) for storing a plurality of pixels from a current video field and a next video field memory (483) for storing a plurality of pixels from a next video field. In a similar manner, the shadow memory (49) comprises a previous-copy video field memory (491), a current-copy video field memory (492), and a next-copy video field memory (493).

Abstract: A single instruction multiple data (SIMD) processor (1) comprises a processing element array (10) including a plurality of processing elements (PEO . . . PEN), and a memory array (14) operably divided into memory portions (141 . . . 14N), each memory portion being assigned to a particular processing element. A first processing element (PEN) is operable to access a portion of the memory array (14) assigned to that first processing element and also to access a portion of the memory array assigned to a second processing element. Such access is made using an index value indicative of the processing element assigned to the memory position to be accessed.

Abstract: An integrated circuit arrangement has a processor array (2) with processor elements (4) and a memory (6) with memory elements (8) arranged in rows (32) and columns (30). The columns (30) of memory elements (8) are addressed by respective processor elements (4). An input sequencer (14) and feedback path (24) cooperate to reorder input data in the memory (6) to carry out both block and line based processing.

Abstract: A single instruction multiple data (SIMD) processor (1) comprises a processing element array (10) including a plurality of processing elements (PEO . . . PEN), and a memory array (14) operably divided into memory portions (141 . . . 14N), each memory portion being assigned to a particular processing element. A first processing element (PEN) is operable to access a portion of the memory array (14) assigned to that first processing element and also to access a portion of the memory array assigned to a second processing element. Such access is made using an index value indicative of the processing element assigned to the memory position to be accessed.

Abstract: A processor array has processor elements (2) and a memory (4), connected in parallel to the accessible in parallel by the processor elements (2). A separate serial module (30) provides additional functionality for example in the form of a look up table module (30). The serial module (3) processes lines of data input to the module (30) serially. Processing can continue in the processor elements (2) in parallel using suitable programming steps.

Abstract: The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and different operand data of the instructions to respective ones of the processing elements (10). Under control of the instructions each processing element (10) determines, whether an operand data dependent condition has occurred. The processing element outputs a condition signal dependent on said determination. The condition signals are summed to form a sum signal. Program flow is controlled by a conditional jump dependent on a value represented by the sum signal.

Abstract: A SIMD processor architecture (2) for processing a stream of data vectors is provided, the architecture comprising a processor array (4) comprising a plurality of processors (PE(0), . . . , (PE(N)), each processor ((PE(0), . . . PE(N)) being adapted to process a data element in each vector, the operation of the processor array (4) being controlled by a local clock signal having a first frequency; a control processor (16) adapted to control the operation of the SIMD processor architecture (2) and generate signals to synchronise the operation of the processor array (4) with the stream of data vectors, the operation of the control processor (16) being controlled by a local clock signal having a second frequency; and power management means (30) for adjusting the frequencies of the local clock signals in response to the synchronisation signals generated by the control processor (16), thereby minimising the power consumption of the SIMD processor architecture (2).

Abstract: A processing element (1) forming part of a parallel processing array such as SIMD comprises an arithmetic logic unit (ALU) (3), a multiplexer (MUX) (5), an accumulator (ACCU) (7) and a flag register (FLAG) (9). The ALU is configured to operate on a common instruction received by all processing elements in the processing array. The processing element (1) further comprises a storage element (SE) (11), which supports the processing of local customized (i.e. data dependent) processing in the processing element (1), such as lookup table operations and the storing local coefficient data.