Abstract: A digital data demodulator employs a cordic rotator-based, digital phase locked loop for carrier frequency tracking. Digitized I and Q channels downconverted to baseband using a fixed frequency oscillator are coupled to a digital cordic rotator. The cordic rotator iteratively executes pipelined phase-rotational adjustments of its digitized in-phase and quadrature inputs, in association with a pipelined reduction of the accumulated value of a phase angle vector code generated by digital phase error detection logic circuitry to which rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values that reduce the accumulated phase error to zero.

Abstract: A system for recovering a payload data stream from a framing data stream utilizes a buffer, a first counter, a second counter, and a clock synchronization element. The buffer is configured to receive the framing data stream and to store payload bits of the framing data stream. The buffer is further configured to transmit the payload bits based on a clock signal. The first counter is configured to produce a first value and to update the first value for each of the payload bits stored in the buffer. The second counter is configured to produce a second value and to update the second value based on the clock signal. The clock synchronization element is coupled to the first and second counters. The clock synchronization element is configured to compare the first and second values and to control a frequency of the clock signal based on comparisons of the first and second values.

Abstract: A digital data demodulator employs a cordic rotator-based, digital phase locked loop for carrier frequency tracking. Digitized I and Q channels downconverted to baseband using a fixed frequency oscillator are coupled to a digital cordic rotator. The cordic rotator iteratively executes pipelined phase-rotational adjustments of its digitized in-phase and quadrature inputs, in association with a pipelined reduction of the accumulated value of a phase angle vector code generated by digital phase error detection logic circuitry to which rotated I and Q outputs of the cordic rotator are applied. The phase error representative code vector is coupled through a digital loop filter as a reference angle input to the cordic rotator. The cordic rotator iteratively rotates the I and Q channel values that reduce the accumulated phase error to zero.

Abstract: A spread spectrum communication system for wirelessly transporting autonomously time-referenced telecommunication data couples the data streams to mutually synchronized multiplexers, outputs of which are encoded and applied to associated I and Q channel spreaders, which spread the respective multiplexed data streams using mutually orthogonal spreading code sequences. The resulting spread I-channel data streams are coupled to I and Q channel summing units outputs of which are applied to respective channels of a QPSK modulator and transmitted to a receiver site. At the receiver the QPSK signals are correlated in despreading correlators and then decoded and demultiplexed to produce data streams, corresponding to those applied to the transmitter.