Patents by Inventor Anthony Aipperspach
Anthony Aipperspach has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070044049Abstract: An apparatus and methods for predicting and/or for calibrating memory yields due to process defects and/or device variations, including determining a model of a memory cell, identifying a subset of parameters associated with the model, determining and executing a refined model using the parameters, determining a predicted probability the simulated memory cell will be operational based on the simulated operation of the refined model, determining yield prediction information from the predicted probability, and determining the minimum number of repair elements to include in a memory array design to insure a desired yield percentage based on the yield prediction information.Type: ApplicationFiled: August 18, 2005Publication date: February 22, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Adams, Anthony Aipperspach, George Paulik
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Publication number: 20070019461Abstract: In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors adapted to both store the bit and affect a signal asserted during a read operation on a bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the group of transistors affects the signal asserted during the read operation on the bit line coupled to the cell. Numerous other aspects are provided.Type: ApplicationFiled: July 21, 2005Publication date: January 25, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Chad Adams, Anthony Aipperspach, Juergen Pille, Otto Wagner
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Publication number: 20070019454Abstract: A glitch protect valid cell and method for maintaining a desired logic state value in response to a glitch signal and a timing signal. The glitch protect valid cell may be integrated with a content addressable memory (CAM) array for indicating whether word data stored within the CAM is valid. The glitch protect valid cell includes a memory element, a state machine, and a glitch protect circuit each responsive to one another. The glitch protect circuit includes a propagation delay assembly and a restore assembly electrically coupled to one another. The propagation delay assembly includes a first pull down network and a NOR gate electrically coupled to one another. The restore assembly includes a second pull down network electrically coupled to the propagation delay assembly. The first pull down network is responsive to the glitch signal and the timing signal to selectively engage the NOR gate.Type: ApplicationFiled: July 19, 2005Publication date: January 25, 2007Applicant: International Business Machines (IBM) CorporationInventors: Derick Behrends, Chad Adams, Ryan Kivimagi, Anthony Aipperspach, Robert Krentler
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Publication number: 20060250842Abstract: In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a first group of transistors adapted to store the bit and a second group of transistors adapted to affect a signal asserted during a read operation on a read bit line coupled to the cell such that the affected signal matches a value of the bit stored in the cell; and (2) preventing the value of the bit stored in the cell from changing state while the second group of transistors affects the signal asserted during the read operation on the read bit line coupled to the cell. Numerous other aspects are provided.Type: ApplicationFiled: May 5, 2005Publication date: November 9, 2006Applicant: International Business Machines CorporationInventors: Chad Adams, Anthony Aipperspach
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Publication number: 20060156091Abstract: In a first aspect, a first method is provided that includes the steps of (1) transmitting a first signal representative of a test operation from a test circuit to a memory via a first signal path; (2) transmitting a second signal, synchronized with the first signal, from the test circuit to the memory via a second signal path; and (3) initiating the test operation on the memory in response to the second signal arriving at the memory. Numerous other aspects are provided.Type: ApplicationFiled: December 28, 2004Publication date: July 13, 2006Applicants: International Business Machines Corporation, Toshiba America Electronic Components, Inc, Kabushiki Kaisha ToshibaInventors: Anthony Aipperspach, Louis Bushard, Akihiko Fukui, Garrett Koch
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Publication number: 20060044020Abstract: A latching dynamic logic includes a dynamic logic gate, a static logic input interface, and a set-reset output latch. The dynamic logic gate receives a clock signal, a data signal, and a select signal output of the static logic input interface. The dynamic logic gate includes a dynamic node and a pulldown network coupled to the dynamic node. The pulldown network selectively discharges the dynamic node following a clock signal transition dependent on the data signal and the select signal output of the static logic input interface being active. The set-reset output latch is coupled to the dynamic node of the dynamic logic gate for providing an output signal.Type: ApplicationFiled: August 26, 2004Publication date: March 2, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Aipperspach, Peter Freiburger
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Publication number: 20050134360Abstract: Methods and apparatus are disclosed that allow an electronic system implemented with field effect transistors (FETs) to reduce threshold voltage shifts caused by bias temperature instability (BTI). BTI caused VT shifts accumulate when an FET is in a particular voltage stress condition. Many storage elements in an electronic system store the same data for virtually the life of the system, resulting in significant BTI caused VT shifts in FETs in the storage elements. An embodiment of the invention ensures that a particular storage element is in a first state for a first portion of time the electronic system operates, during which data is stored in a storage element in a first phase, and that the particular storage element is in a second state for a second portion of time the electronic system operates, during which data is stored in the storage element in a second phase.Type: ApplicationFiled: December 23, 2003Publication date: June 23, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Aipperspach, William Hovis, Terrance Kueper, John Sheets
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Publication number: 20050091620Abstract: The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.Type: ApplicationFiled: October 23, 2003Publication date: April 28, 2005Applicant: International Business Machines CorporationInventors: Anthony Aipperspach, David Boerstler, Eskinder Hailu
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Publication number: 20050066253Abstract: Detection of multiple data bit errors in physically adjacent data bits in a memory boundary having a parity bit, comprising activating each of a line of a memory boundary in a memory array having the parity bit; and, directing physically adjacent data bits in an activated line to two or more parity checking devices so that two or more physically adjacent data bits are not forwarded to the same one the two or more parity checking devices.Type: ApplicationFiled: September 18, 2003Publication date: March 24, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Aipperspach, Todd Christensen, Mydung Pham
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Publication number: 20050010885Abstract: A method and an apparatus are provided for limiting a pulse width in a chip clock design of a circuit. The circuit receives a clock signal having a clock pulse width. The clock pulse width of the clock signal is detected. It is determined whether the clock pulse width is larger than a maximum clock pulse width. Upon a determination that the clock pulse width is larger than a maximum clock pulse width, the clock pulse width of the clock signal is limited.Type: ApplicationFiled: July 10, 2003Publication date: January 13, 2005Applicant: International Business Machines CorporationInventors: Anthony Aipperspach, David Boerstler, Dieter Wendel
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Publication number: 20050007813Abstract: The present invention provides for reading indicia from an SRAM cell. A low value is generated on a write true line. A high value is generated on a continuous bit_line. The true node of the SRAM cell is evaluated through use of a floating voltage coupled to the true node of the SRAM cell. If the floating voltage stays substantially constant, the value read from the SRAM cell is a high. If the floating voltage is drained to ground, the value read from the SRAM cell is a low.Type: ApplicationFiled: July 10, 2003Publication date: January 13, 2005Applicant: International Business Machines CorporationInventors: Chad Adams, Anthony Aipperspach, Todd Christensen, Peter Freiburger