Abstract: A processing system employs system hardware to secure different DRM channels. The processing system employs an architecture including a root-of-trust (RoT) processor that assigns different keyspaces to different DRM channels. The processing system further includes one or more security gaskets that employ the assigned keyspaces to isolate the different DRM channels from each other. The security gasket receives a transaction targeting a DRM pipeline and allows the transaction to proceed based on a keyspace identified by the transaction and a keyspace assigned to the DRM.

Abstract: The disclosed circuit can select a key index in response to a memory request including a physical address. The physical address points to a location of a graphics processing unit memory that is encrypted. The circuit can forward the selected key index with the physical address to a memory controller of the graphics processing unit memory. The memory controller can complete the memory request using a key associated with the key index. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed computer-implemented method can include reaching, by a chiplet involved in carrying out an operation for a process, a synchronization barrier. The method can additionally include receiving, by the chiplet, dedicated control messages pushed to the chiplet by other chiplets involved in carrying out the operation for the process, wherein the dedicated control messages are pushed over a control network by the other chiplets. The method can also include advancing, by the chiplet, the synchronization barrier in response to receipt of the dedicated control messages. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: The disclosed device includes a direct memory access (DMA) engine having multiple backends and a frontend. The frontend receives a memory operation command, selects one of the backends based on an affinity of the selected backend corresponding to the memory operation command, and instructing the selected backend to perform the memory operation command. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An apparatus and method for efficiently performing remote memory access requests among multiple processing nodes. In various implementations, a computing system has a first node and a second node. Each of these nodes has a corresponding virtual address space in the computing system, and each node assigns subdivisions of the virtual address spaces to multiple clients of the node. The nodes assign a subset of a first virtual address space of a first client in the first node to remote data stored in a second virtual address space of a second client in the second node. Remote presence check (RPC) circuits of the nodes assign the second virtual address space to a subset of a network physical address (NPA) space. The RPC circuits of the nodes use assignments to the NPA space to verify that address mappings in TLBs are still available prior to routing memory access requests.

Abstract: The disclosed device includes a control circuit that translates a virtual address to a final physical address for a graphics processing unit memory. The control circuit can confirm that a guest making the translation request has ownership of the final physical address and return the final physical address if the translation request passes the ownership checks. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

Abstract: A processor supports secure memory access in a virtualized computing environment by employing requestor identifiers at bus devices (such as a graphics processing unit) to identify the virtual machine associated with each memory access request. The virtualized computing environment uses the requestor identifiers to control access to different regions of system memory, ensuring that each VM accesses only those regions of memory that the VM is allowed to access. The virtualized computing environment thereby supports efficient memory access by the bus devices while ensuring that the different regions of memory are protected from unauthorized access.

Abstract: An apparatus and method for efficiently accessing hardware resources in a virtualized environment. In various implementations, a computing system includes a first processing circuit and a second processing circuit that is a parallel data processing circuit. The second processing circuit includes multiple subdivisions, each with compute circuits, a memory subsystem, and a command processing circuit. The hypervisor running on the first processing circuit divides the second processing circuit into multiple partitions, each with a guest operating system and one or more subdivisions. A single mapping of multiple mappings includes a virtual function identifier that specifies a guest operating system, a virtual hardware resource identifier, and a corresponding physical hardware resource identifier. The hypervisor sends the mappings to at least the second processing circuit that uses the mappings to perform translations during execution of tasks. The first processing circuit does not perform translations.

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

Abstract: A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Abstract: Systems and methods for dynamic repartitioning of physical memory address mapping involve relocating data stored at one or more physical memory locations of one or more memory devices to another memory device or mass storage device, repartitioning one or more corresponding physical memory maps to include new mappings between physical memory addresses and physical memory locations of the one or more memory devices, then loading the relocated data back onto the one or more memory devices at physical memory locations determined by the new physical address mapping. Such dynamic repartitioning of the physical memory address mapping does not require a processing system to be rebooted and has various applications in connection with interleaving reconfiguration and error correcting code (ECC) reconfiguration of the processing system.

Abstract: The disclosed device includes a device comprising a device-attached memory and a trust controller for confidential computing. The trust controller can maintain a record of devices that are permitted to access the device-attached memory, receive updates to the record, and verify, based on the record, attempts to access the memory.

Abstract: In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.

Abstract: A method and system for providing memory in a computer system. The method includes receiving a memory access request for a shared memory address from a processor, mapping the received memory access request to at least one virtual memory pool to produce a mapping result, and providing the mapping result to the processor.

Abstract: Systems and techniques enable intermingled use of disparate addressing modes for memory access requests directed to system memory resources. Within a processing system, a memory access request indicating a multi-bit physical memory address is received. Based on a bit pattern indicated by a first subset of bits of the multi-bit physical memory address, an addressing mode to be used for fulfilling the memory access request is determined, such as by selecting an addressing mode table entry that is keyed to the bit pattern. The memory access request is fulfilled in accordance with the determined addressing mode.

Abstract: A method and apparatus of managing memory includes storing a first memory page at a shared memory location in response to the first memory page including data shared between a first virtual machine and a second virtual machine. A second memory page is stored at a memory location unique to the first virtual machine in response to the second memory page including data unique to the first virtual machine. The first memory page is accessed by the first virtual machine and the second virtual machine, and the second memory page is accessed by the first virtual machine and not the second virtual machine.

Abstract: An apparatus and method for efficiently performing address translation requests. An integrated circuit includes a system memory that stores address mappings, and the circuitry of one or more clients processes one or more applications and generate address translation requests. A translation lookaside buffer (TLB) stores, in multiple entries, address mappings retrieved from the system memory. Circuitry of a client processes one or more applications and generates address translation requests. The entries of the TLB stores address mappings corresponding to different address mapping types and different virtual functions to avoid searches of multiple other lower-level TLBs that are significantly larger and have larger access. In addition, the TLB is implemented with a relatively small number of entries and uses fully associative data storage arrangement to further reduce access latencies.

Abstract: A processing system including a parallel processing unit selectively allocating pages of memory for interleaving across configurable subsets of channels based on a mode of allocation. In some embodiments, in a first mode, a page of memory is allocated to and interleaved across a plurality of channels, and in a second mode, a page of memory is allocated to and interleaved across a subset of the plurality of channels.

Abstract: In accordance with the described techniques for extended attributes for shared page tables, a device includes an accelerator device and a memory management unit that maintains a first set of page tables and a second set of page tables. The second set of page tables includes extended attributes for accessing data that the accelerator device operates on. The memory management unit is configured to receive a virtual memory address, and translate the virtual memory address to a physical memory address using the first set of page tables. In addition, the memory management unit retrieves the extended attributes from the second set of page tables. In this way, data is accessed from the physical memory address based on the extended attributes.