Abstract: Disclosed herein are systems, apparatuses, and methods for enabling efficient reads to a local memory of a processing unit. In an embodiment, a processing unit includes an interface and a buffer. The interface is configured to (i) send a request for a portion of data in a region of a local memory of an other processing unit and (ii) receive, responsive to the request, all the data from the region. The buffer is configured to store the data from the region of the local memory of the other processing unit.

Abstract: Methods and apparatus for translating messages in a computing system are disclosed. In particular, a disclosed method for converting messages in a computer system includes receiving a command message from a processing unit where the message is defined according to a transport protocol that utilizes command messages using an address to communicate commands to devices in the computer system. The command message is translated to an interface standard by mapping the address into an address field of a packet constructed according to the interface standard. Corresponding apparatus that perform the methods are also disclosed.

Abstract: A method for determining an operating point of a shared resource. The method includes receiving indications of access demand to a shared resource from each of a plurality of functional units and determining a maximum access demand from among the plurality of functional units based on their respective indications. The method further includes determining a required operating point of the shared resource based on the maximum access demand, wherein the shared resource is shared by each of the plurality of functional units, comparing the required operating point to a present operating point of the shared resource, and changing to the required operating point from the present operating point if the required and present operating points are different.

Abstract: Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. A method includes generating a memory write request in a second protocol responsive to a memory write request of a first protocol, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The method also includes inserting a predefined code in the memory write request in the generated memory write request in the second protocol to produce a translated memory write request. The method may also include receiving the memory write request from the first processor where the memory write request is operable according to the first protocol having at least first and second memory write command types.

Abstract: A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the IO controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory.

Abstract: A circuit includes a high priority circuit and a non-high priority circuit. The high priority circuit is operative to communicate high priority information to a single path of a differential serial communication link. The non-high priority circuit communicates non-high priority information to the single path. The high priority information is communicated prior to the non-high priority information. In one example, the circuit includes a flow control distributor operatively coupled to the high priority circuit and the non-high priority circuit. The flow control distributor distributes a total number of flow control credits into high priority credits and non-high priority credits. The flow control distributor controls communication of the high priority information based on the high priority credits. The flow control distributor controls communication of the non-high priority information based on the non-high priority credits.

Abstract: A method and apparatus stores data representing a non 1:1 memory access interleaving ratio for accessing a plurality of memories. The method and apparatus interleaves memory accesses to at least either a first memory that is accessible via a first (and associated memory) bus having first characteristics or a second memory accessible via a second bus having different characteristics, based on the data representing the non 1:1 interleaving memory access ratio.

Abstract: Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write request directed to a memory address and generates a plurality of graphics device addresses based on the memory address of the write request when the memory address is within a particular range of broadcast addresses. An offset may be applied to a reference address in each address range associated with one of the graphics devices when generating the plurality of graphics device addresses. The write request is forwarded to each graphics device of the plurality of graphics devices associated with one of the generated graphics device addresses.

Abstract: Methods and apparatus for translating messages in a computing system are disclosed. In particular, a disclosed method for converting messages in a computer system includes receiving a command message from a processing unit where the message is defined according to a transport protocol that utilizes command messages using an address to communicate commands to devices in the computer system. The command message is translated to an interface standard by mapping the address into an address field of a packet constructed according to the interface standard. Corresponding apparatus that perform the methods are also disclosed.

Abstract: Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. A method includes generating a memory write request in a second protocol responsive to a memory write request of a first protocol, the first protocol supporting a first memory write command type and a second memory write command type, the second protocol supporting only the first memory write command type. The method also includes inserting a predefined code in the memory write request in the generated memory write request in the second protocol to produce a translated memory write request. The method may also include receiving the memory write request from the first processor where the memory write request is operable according to the first protocol having at least first and second memory write command types.

Abstract: A method and apparatus for data bus inversion provides for a data bus having a data bus size value, wherein the data bus size value represents the number of bits transferred across the bus in a single transmission, for receiving a new data value having a plurality of new data bits. The method and apparatus further provide for determining the change bit value by comparing the different new data bits with a plurality of current transmission data bits from a current data value. Furthermore, when the change bit value is equal to one-half the data bus size value, the method and apparatus provides for adjusting at least the plurality of new data bits and/or a data bus inversion bit, based on the determination to assert the plurality of new data bits and the data bus inversion bit closer to a bus idle value.

Abstract: A method and apparatus for a processing system to utilize a ring buffer includes a host processor, memory, and at least one co-processor. The host processor generates a plurality of data blocks that relates to a particular application (e.g., word processing application, drafting application, presentation application, spreadsheet application, video game application, etc.). The host processor writes data elements of the data blocks into the memory, which is organized in a ring buffer manner. As the host processor enters the data elements into the ring buffer, it updates a head pointer, which indicates the most current address of a data element entered into the ring buffer, in its local cache. The co-processor retrieves the data elements from the ring buffer and performs a co-processor function in support of the particular application.

Abstract: A method and apparatus for co-processing multi-formatted data which begins when a host processor writes data blocks, in a substantially continuous manner, into memory. Each of the data blocks includes a plurality of data elements and each data element has one of a plurality of data formats. As the data block is being stored in memory, a co-processor retrieves selected data elements from the memory. Upon retrieving the selected data elements, the co-processor interprets them to identify the data format. If the data format is consistent with the data format of the co-processor, the co-processor processes the data element without conversion. If, however, the data format of the selected data element is not consistent with the data format of the co-processor, the co-processor converts the format of the selected data element into the format consistent with the co-processor.