Abstract: An improved method and system for development of passive simulation clients includes: running a simulation by a simulator; storing at least a portion of information from the simulation; retrieving the stored information by a simulation proxy; and recreating the simulation by the simulation proxy based on the retrieved information. Full or relevant subset of machine states may be stored in a storage mechanism, which is accessed by the simulation client through the simulation proxy. During code development, instead of accessing the simulator directly, the simulation client code is provided a cycle by cycle view of the simulation model from the storage mechanism as recreated by the simulation proxy. In this manner, development time is quicker as a full simulation environment need not be loaded and run. In addition, machine resources required during client development are reduced drastically.

Abstract: Systems, methods, and media for reconstructing data from simulation models are disclosed. Embodiments may include a method for accessing an alias from an alias file. The method may generally include searching for a net name and, if the net name is not found, searching an alias index file for an alias index entry associated with the net name, the alias index entry having a net name and an associated position. The method may also generally include, if the net name entry is found, accessing from an alias file an alias associated with the net name. A further embodiment of the method may generally include receiving a net name and a position of an alias in the alias file, creating an alias index entry for the alias having a net name and the position of the alias, and storing the created alias index entry in the alias index file.

Abstract: A method and system for reducing overhead on a loop of a plurality of instructions is disclosed. The loop is performed a particular number of times. The method and system include a mask register and addition logic. The mask register provides a carry mask having a first value for the loop being performed at least the particular number of times minus one time and a second value for at least a last instruction of the loop being performed a last time. The addition logic is coupled with the mask register and determines which of the plurality of instructions is to be executed. The carry mask and a current instruction of the plurality of instructions correspond to inputs of the addition logic. A resultant of the addition logic corresponds to a next instruction of the plurality of instructions unless the current instruction is the last instruction.

Abstract: A JTAG-compliant device is configured to receive data through the control (TMS) line in addition to being configured to receive data through the input (TDI) line. A burst-write instruction is made the active instruction, extending the capability of the test access protocol (TAP) controller such that the TAP controller can receive data into a data register while the TAP controller is in certain states. In some states, the TAP controller receives and stores a bit only from the input line. In other states, the TAP controller receives and stores a bit from the input line, and in addition, the TAP controller receives and stores a bit from the control line. The TAP controller may store the received bits by shifting the received bits into the least significant bit of a data register.

Abstract: A method and system for testing a plurality of cores in an integrated circuit is disclosed. The method and system include providing a plurality of slave controllers a master controller. Each of the plurality of slave controllers is for testing at least one of the plurality of cores. The master controller is coupled with the plurality of slave controllers in a star configuration. The master controller is configured to allow test data to be input directly to a portion of the plurality of slave controllers in parallel. The portion of the plurality of slave controllers can include more than one slave controller.