Patents by Inventor Anthony C. Speranza
Anthony C. Speranza has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10607899Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.Type: GrantFiled: January 3, 2017Date of Patent: March 31, 2020Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Jeffrey P. Gambino, Eric A. Joseph, Anthony C. Speranza
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Publication number: 20170117195Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.Type: ApplicationFiled: January 3, 2017Publication date: April 27, 2017Inventors: Shawn A. Adderly, Jeffrey P. Gambino, Eric A. Joseph, Anthony C. Speranza
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Patent number: 9583401Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.Type: GrantFiled: February 12, 2014Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Jeffrey P. Gambino, Eric A. Joseph, Anthony C. Speranza
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Patent number: 9484301Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: GrantFiled: May 21, 2015Date of Patent: November 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Publication number: 20150255395Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Publication number: 20150228548Abstract: An apparatus for and methods of repairing and manufacturing integrated circuits using the apparatus. The apparatus, comprising: a vacuum chamber containing: a movable stage configured to hold a substrate; an inspection and analysis probe; a heat source; a gas injector; and a gas manifold connecting multiple gas sources to the gas injector.Type: ApplicationFiled: February 12, 2014Publication date: August 13, 2015Applicant: International Business Machines CorporationInventors: Shawn A. Adderly, Jeffrey P. Gambino, Eric A. Joseph, Anthony C. Speranza
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Patent number: 9087839Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.Type: GrantFiled: March 29, 2013Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shawn A. Adderly, Daniel A. Delibac, Zhong-Xiang He, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Eric J. White
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Patent number: 9059258Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: GrantFiled: March 4, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Publication number: 20140291802Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shawn A. Adderly, Daniel A. Delibac, Zhong-Xiang He, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Eric J. White
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Publication number: 20140246777Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: ApplicationFiled: March 4, 2013Publication date: September 4, 2014Applicant: International Business Machines CorporationInventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Patent number: 7696037Abstract: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.Type: GrantFiled: August 11, 2008Date of Patent: April 13, 2010Assignee: International Business Machines CorporationInventor: Anthony C. Speranza
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Patent number: 7462528Abstract: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.Type: GrantFiled: June 7, 2007Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventor: Anthony C. Speranza
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Publication number: 20080299721Abstract: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.Type: ApplicationFiled: August 11, 2008Publication date: December 4, 2008Inventor: Anthony C. Speranza
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Patent number: 7271044Abstract: A method for forming semiconductor transistor. The method comprises providing a structure including (a) a semiconductor region, and (b) first and second dopant source regions on and in direct physical contact with the semiconductor region, wherein each region of the first and second dopant source regions comprises a dielectric material which contains dopants; causing the dopants to diffuse from the first and second dopant source regions into the semiconductor region so as to form first and second source/drain extension regions, respectively, wherein the first and second source/drain extension regions define a channel region disposed between; forming a gate dielectric region on a channel region; and forming a gate region on the gate dielectric region, wherein the gate dielectric region electrically insulates the gate region from the channel region.Type: GrantFiled: July 21, 2005Date of Patent: September 18, 2007Assignee: International Business Machines CorporationInventor: Anthony C. Speranza
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Publication number: 20020106906Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.Type: ApplicationFiled: December 13, 2000Publication date: August 8, 2002Applicant: International Business Machines CorporationInventors: Arne W. Ballantine, Jeffrey S. Brown, Jeffrey D. Gilbert, James J. Quinlivan, James A. Slinkman, Anthony C. Speranza
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Patent number: 6417070Abstract: A structure comprising a trench having a liner with rounded corners in the top and bottom of the trench is obtained by rapid thermal oxidation.Type: GrantFiled: December 13, 2000Date of Patent: July 9, 2002Assignee: International Business Machines CorporationInventors: Arne W. Ballantine, Jeffrey S. Brown, Jeffrey D. Gilbert, James J. Quinlivan, James A. Slinkman, Anthony C. Speranza
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Patent number: 6121064Abstract: A method of manufacturing and inspecting SOI such that during STI formation, by depositing a light absorbing layer in the STI such as hydrosilicon oxynitride, the silicon inclusions in the buried insulator layer of the SOI are undetectable by an optical inspection. The reduction in background effects allows for improved optical inspection of SOI wafers without having to discriminate against defects created by SOI formation. A method of manufacturing and inspecting semiconductor devices is disclosed wherein deposition of a light absorbing layer, such as hydrosilicon oxynitride, prevents defects occurring prior to deposition from being optically inspectable and those defects created during the most recent processing can be easily distinguished. Also disclosed are an optically inspectable semiconductor device and an optically inspectable semiconductor device having an STI.Type: GrantFiled: January 4, 1999Date of Patent: September 19, 2000Assignee: International Business Machines CorporationInventors: Jerome B. Lasky, Bret Philips, Anthony C. Speranza, Justin Wong, Mickey H. Yu
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Patent number: 6028339Abstract: A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.Type: GrantFiled: December 14, 1998Date of Patent: February 22, 2000Assignee: International Business Machines CorporationInventors: Robert O. Frenette, Dale P. Hallock, Stephen A. Mongeon, Anthony C. Speranza, William R. P. Tonti
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Patent number: 5985768Abstract: The present invention discloses a method of doping and preventing silicide formation in selective areas of a polysilicon gate in MOS, PMOS, NMOS or CMOS manufacturing technologies. The process includes the steps of: depositing a non-conformal dopant containing layer on the top surface of the body and the top surface of the polysilicon gate; removing a portion of the non-conformal dopant containing layer to expose the top surface of the polysilicon gate; and heating to diffuse dopant from the dopant containing layer. Silicidation is then provided by depositing a metal layer and annealing the metal layer. As a first alternative method, the heating and removing step may be reversed. As a second alternative method, after removal of the non-conformal layer, a metal layer can be deposited followed by a combination anneal of the metal layer and non-conformal dopant containing layer.Type: GrantFiled: April 30, 1997Date of Patent: November 16, 1999Assignee: International Business Machines CorporationInventors: Anthony C. Speranza, Bradley P. Jones
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Patent number: 5770490Abstract: A dual work function CMOS device and method for producing the same is disclosed. The method includes: depositing a first layer of a doped material, either n-type or p-type, over a substrate to be doped; defining the areas that are to be oppositely doped; depositing a second layer of an oppositely doped material over the entire surface; and subjecting the entire CMOS device to a high temperature, drive-in anneal. The drive-in anneal accelerates the diffusion of the dopants into the adjacent areas, thereby doping the gate polysilicon and channels with the desired dopants. A nitride barrier layer may be utilized to prevent the second dopant from diffusing through the first layer and into the substrate beneath.Type: GrantFiled: August 29, 1996Date of Patent: June 23, 1998Assignee: International Business Machines CorporationInventors: Robert O. Frenette, Dale P. Hallock, Stephen A. Mongeon, Anthony C. Speranza, William R. P. Tonti