Patents by Inventor Anthony Chou
Anthony Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240122551Abstract: A wearable device utilizing flexible electronics is disclosed. The wearable device may comprise a flexible matrix material and may include sensors for measuring biometric measurements of an individual, an accelerometer for measuring an acceleration of a body part to which the wearable device is attached, a wireless transmitter, a flexible power source, and a microcontroller. During an activity, the microcontroller may receive signals from the sensors including the biometric measurements, and signals from the accelerometer including acceleration and force measurements associated with the individual. The microcontroller may convert the signals into digital signals and transmit the signals to a computing device for analysis. The computing device may analyze the digital signals to determine a performance metric for the individual. The performance metric may be compared to baseline data for the individual to determine a fatigue level, injury risk, or an adjustment to be made by the individual during the activity.Type: ApplicationFiled: December 4, 2023Publication date: April 18, 2024Inventors: Ricky ALPHONSE, Kelsey MELROSE, Catherine CHOU, Noah SCHIMMEL, Ramamurthy SIRIPURAM, Anthony TRAN, Britny FARAHDEL, Dalton SMITH, Danice WANG, Kunal MEHAN, Theodore VIRTUE
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Patent number: 10014364Abstract: Device structures and fabrication methods for an on-chip resistor. A first Seebeck terminal is arranged to overlap with first and second resistor bodies of the on-chip resistor. A second Seebeck terminal is also arranged to overlap with the first and second resistor bodies. The second Seebeck terminal has a spaced relationship with the first Seebeck terminal along a length of the first and second resistor bodies. The temperature coefficient of resistance of the on-chip resistor is based at least in part on a Seebeck coefficient of first and second Seebeck terminals.Type: GrantFiled: March 16, 2017Date of Patent: July 3, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Qun Gao, Anthony Chou, Stephen Furkay, Naved Siddiqui
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Publication number: 20120146811Abstract: A driving assisting system includes a traffic signal controller, an RSU, at least one data transmission interface and an OBU. The RSU is electrically connected to the traffic signal controller. The OBU is installed on a vehicle. The traffic signal controller controls a traffic light, which is located at an intersection. The RSU obtains traffic-light information of the traffic light from the traffic signal controller. The OBU receives the traffic-light information through the at least one data transmission interface from the RSU. The OBU generates dynamic vehicle information of the vehicle. The OBU determines if the vehicle will be positioned at a key zone of the intersection when the traffic light switches according to the dynamic vehicle information and the traffic-light information. The OBU responds according to a key zone type of the key zone when the vehicle is positioned at the key zone of the intersection.Type: ApplicationFiled: May 2, 2011Publication date: June 14, 2012Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Anthony CHOU, Yen-Ning LEE, Cheng-Hsuan CHO, Tang-Hsien CHANG, Shang-Min YU, Chia-Hung CHUEH
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Publication number: 20120123894Abstract: A method for decentralized transportation dispatching is disclosed. The method bypasses utilizing a centralized dispatch call center and includes announcing a transportation requirement via broadcasting directly by at least one user, and replying to the transportation requirement with a plurality of competitive bidding information directly from a plurality of transportation providers who are capable of providing a passenger-carrying service or providing a goods-carrying service. The method further includes selecting one transportation provider from the transportation providers according to a request from the user, in which the selecting is performed through referencing the bidding information replied to by the transportation providers.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: INSTITUTE FOR INFORMATION INDUSTRYInventors: Frank Chee-Da Tsai, Anthony Chou, Wen-Yao Chang
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Publication number: 20110284932Abstract: A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact.Type: ApplicationFiled: May 18, 2010Publication date: November 24, 2011Applicant: INERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony CHOU, Arvind KUMAR, Shreesh NARASIMHA
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Patent number: 8053325Abstract: A body contact structure which reduce parasitic capacitance and improves body resistance of a device and methods of manufacture. The method includes forming a gate insulator material and gate electrode material on a substrate. The method further includes patterning the gate insulator material and the gate electrode material to form a gate structure having a shape with a first portion isolated from a second portion. The method further includes forming source and drain regions on sides of the first portion and a body contact at a side and under an area of the second portion, and forming an interlevel dielectric within a space that isolates the first portion from the second portion of the gate structure, and over the gate structure, source and drain regions and the body contact.Type: GrantFiled: May 18, 2010Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Anthony Chou, Arvind Kumar, Shreesh Narasimha
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Patent number: 7705385Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: GrantFiled: September 12, 2005Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Ashima Chakravarti, Anthony Chou, Toshiharu Furukawa, Steven Holmes, Wesley Natzle
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Publication number: 20080090379Abstract: A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure.Type: ApplicationFiled: December 13, 2007Publication date: April 17, 2008Applicant: International Business Machines CorporationInventors: Fred Buehrer, Anthony Chou, Toshiharu Furukawa, Renee Mo
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Patent number: 7235440Abstract: Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.Type: GrantFiled: July 31, 2003Date of Patent: June 26, 2007Assignees: Tokyo Electron Limited, International Business Machines CorporationInventors: David L O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
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Patent number: 7202186Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.Type: GrantFiled: July 31, 2003Date of Patent: April 10, 2007Assignees: Tokyo Electron Limited, International Business Machines Corporation (IBM)Inventors: David L O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
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Publication number: 20070059894Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: ApplicationFiled: September 12, 2005Publication date: March 15, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima Chakravarti, Anthony Chou, Toshiharu Furukawa, Steven Holmes, Wesley Natzle
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Publication number: 20070010050Abstract: The present invention provides methods for forming semiconductor FET devices having reduced gate edge leakage current by using plasma or thermal nitridation and low-temperature plasma re-oxidation processes post gate etch.Type: ApplicationFiled: July 6, 2005Publication date: January 11, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony Chou, Shreesh Narasimha
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Publication number: 20060160322Abstract: A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure.Type: ApplicationFiled: January 17, 2005Publication date: July 20, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fred Buehrer, Anthony Chou, Toshiharu Furukawa, Renee Mo
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Publication number: 20060057811Abstract: A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.Type: ApplicationFiled: November 7, 2005Publication date: March 16, 2006Applicant: International Business Machines CorporationInventors: Anthony Chou, Toshiharu Furukawa, Steven Holmes
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Publication number: 20050148144Abstract: A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.Type: ApplicationFiled: December 10, 2003Publication date: July 7, 2005Applicant: International Business Machines CorporationInventors: Anthony Chou, Toshiharu Furukawa, Steven Holmes
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Publication number: 20050118836Abstract: Methods for forming an oxynitride dielectric in a semiconductor device are disclosed. In the method, an oxynitride layer is grown on a semiconductor device. The oxynitride layer is then annealed at a temperature of about 400° C. for about 20 minutes. Further, the annealing may be performed in a nitrogen ambient or a nitrogen ambient including an oxygen concentration of less than about 1 to about 10 parts per billion.Type: ApplicationFiled: December 2, 2003Publication date: June 2, 2005Inventors: Anthony Chou, Robert Laibowitz
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Publication number: 20050118764Abstract: Gate oxides having different thicknesses are formed on a semiconductor substrate by forming a first gate oxide on the top surface of the substrate, forming a sacrificial hard mask over a selected area of the first gate oxide; and then forming a second gate oxide. A first poly layer may be formed on the first gate oxide, under the hard mask. After the hard mask is removed, a second poly layer may be formed over the second gate oxide and over the first poly layer. This enables the use of high-k dielectric materials, and the first gate oxide can be thinner than the second gate oxide.Type: ApplicationFiled: November 28, 2003Publication date: June 2, 2005Inventors: Anthony Chou, Michael Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul Kirsch, Byoung Lee, Katsunori Onishi, Heemyoung Park, Kristen Scheer, Akihisa Sekiguchi
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Publication number: 20050026459Abstract: Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Applicants: Tokyo Electron Limited, International Business Machines CorporationInventors: David O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins
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Publication number: 20050026453Abstract: Ultra-thin oxide layers are formed utilizing low pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxide. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, a nitride layer, a high-k layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or, alternatively, using a single-wafer process chamber. One embodiment of the invention provides self-limiting oxidation of Si-substrates that results in SiO2 layers with a thickness of about 15 A, where the thickness of the SiO2 layers varies less than about 1 A over the substrates.Type: ApplicationFiled: July 31, 2003Publication date: February 3, 2005Applicants: Tokyo Electron Limited, International Business Machines CorporationInventors: David O'Meara, Cory Wajda, Anthony Dip, Michael Toeller, Toshihara Furukawa, Kristen Scheer, Alessandro Callegari, Fred Buehrer, Sufi Zafar, Evgeni Gousev, Anthony Chou, Paul Higgins