Patents by Inventor Anthony D. Nguyen

Anthony D. Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Vector instructions to enable efficient synchronization and parallel reduction operations
    Patent number: 9678750
    Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: June 13, 2017
    Assignee: Intel Corporation
    Inventors: Mikhail Smelyanskiy, Victor Lee, Christopher Hughes, Daehyun Kim, Yen-Kuang Chen, Changkyu Kim, Jatin Chhugani, Anthony D. Nguyen, Sanjeev Kumar
  • Vector instructions to enable efficient synchronization and parallel reduction operations
    Patent number: 9513905
    Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 28, 2008
    Date of Patent: December 6, 2016
    Assignee: Intel Corporation
    Inventors: Mikhail Smelyanskiy, Sanjeev Kumar, Daehyun Kim, Jatin Chhugani, Changkyu Kim, Christopher J. Hughes, Victor W. Lee, Anthony D. Nguyen, Yen-Kuang Chen
  • VECTOR INSTRUCTIONS TO ENABLE EFFICIENT SYNCHRONIZATION AND PARALLEL REDUCTION OPERATIONS
    Publication number: 20140068226
    Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
    Type: Application
    Filed: March 12, 2013
    Publication date: March 6, 2014
    Inventors: MIKHAIL SMELYANSKIY, VICTOR LEE, CHRISTOPHER HUGHES, DAEHYUN KIM, YEN-KUANG CHEN, CHANGKYU KIM, JATIN CHHUGANI, ANTHONY D. NGUYEN, SANJEEV KUMAR
  • Vector instructions to enable efficient synchronization and parallel reduction operations
    Publication number: 20090249026
    Abstract: In one embodiment, a processor may include a vector unit to perform operations on multiple data elements responsive to a single instruction, and a control unit coupled to the vector unit to provide the data elements to the vector unit, where the control unit is to enable an atomic vector operation to be performed on at least some of the data elements responsive to a first vector instruction to be executed under a first mask and a second vector instruction to be executed under a second mask. Other embodiments are described and claimed.
    Type: Application
    Filed: March 28, 2008
    Publication date: October 1, 2009
    Inventors: Mikhail Smelyanskiy, Sanjeev Kumar, Daehyun Kim, Jatin Chhugani, Changkyu Kim, Christopher J. Hughes, Victor W. Lee, Anthony D. Nguyen, Yen-Kuang Chen
  • Technique to perform concurrent updates to a shared data structure
    Patent number: 7350036
    Abstract: A technique to perform concurrent updates to a shared data structure. At least one embodiment of the invention concurrently stores copies of a data structure within a plurality of local caches, updates the local caches with a partial result of a computation distributed among a plurality of processing elements, and returns the partial results to combining logic in parallel, which combines the partial results into a final result.
    Type: Grant
    Filed: August 1, 2005
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Daehyun Kim, Victor W. Lee, Anthony D. Nguyen, Mikhail Smelyanskiy