Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.

Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.

Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter. Improved memory addressing means facilitates altering the spark advance in accordance with a sensed condition such as manifold vacuum, and conserves memory space.

Abstract: A means to set spark timing in accordance with engine speed includes a counter to count clock pulses between engine speed reference pulses. A read-only memory has successive memory locations each storing an addend quantity and a repeats number. An adder unit, including an accumulator, operates to access the memory locations, and to add the addend quantities to the contents of the accumulator repeatedly a number of times equal to the respective repeats numbers. A comparator produces an ignition firing pulse when the contents of the accumulator corresponds with the reference period number provided by the counter.

Abstract: A digital drive current for application to a variable-speed electric motor is generated from a binary signal including N high-order bits and n low-order bits. A pulse waveform of fixed frequency higher than the frequency to which the motor can respond is generated to have a pulse width duty cycle in accordance with the value of the high-order bits. The low-order bits are used to make a one-step increase in the width of a proportion, determined by the value of the low-order bits, of the pulses of the pulse waveform, so that the average pulse width is increased a desired fraction of one step.

Abstract: An improved circuit for measuring resistance, as for the resistance of a temperature sensor, wherein the resistance varies over a wide dynamic range. The circuit provides two switch means to charge two capacitors through the unknown resistance. A time interval means measures charging time for one or both capacitors. Since charging time is directly proportional to resistance, a value of resistance is computed for one or both charging times. Control means, responsive to the time interval means, is provided to sequentially operate one or both switch means, the control means including means for selecting that charging time which is as long as possible yet within the range of the time interval means, thereby obtaining a higher resolution measurement in the range of sensor resistance where resolution would otherwise be inadequate.

Abstract: A signal sampling circuit is disclosed which accommodates itself to operation during the presence of high noise levels encountered, for example, when attempting to monitor and control, and thus optimize, the functioning of an internal combustion engine. Noise detection means is provided for detecting the presence or absence of noise pulses during either a request for a signal sample or during a signal sampling period. When the noise detector indicates the presence of noise during the request or during the sampling period, the derived information is disregarded and either reread during the next, noise-free period or is resampled shortly after the sampling interval in which the discarded information was obtained.