Abstract: A method for providing high-speed storage and retrieval of information from a plurality of sources is disclosed. The method includes retrieving data from the sources; identifying a deterministic perfect hash function based on the retrieved data for stock symbols and corresponding stock information, the perfect hash function relating to a mapping of distinct elements in the corresponding stock information with the stock symbols; generating, by using the retrieved data, a parameter that relates to an instruction to calculate the identified perfect hash function, the parameter including a host file, a simulation file, and a hash state file; programming a register and a memory that are associated with the processor by using the parameter; and determining, via the programmed register and the programmed memory, a hash value for incoming stock symbols, the hash value relating to a symbol index that locates information corresponding to the incoming stock symbols.

Abstract: A method for providing high-speed storage and retrieval of information from a plurality of sources is disclosed. The method includes retrieving data from the sources; identifying a deterministic perfect hash function based on the retrieved data for stock symbols and corresponding stock information, the perfect hash function relating to a mapping of distinct elements in the corresponding stock information with the stock symbols; generating, by using the retrieved data, a parameter that relates to an instruction to calculate the identified perfect hash function, the parameter including a host file, a simulation file, and a hash state file; programming a register and a memory that are associated with the processor by using the parameter; and determining, via the programmed register and the programmed memory, a hash value for incoming stock symbols, the hash value relating to a symbol index that locates information corresponding to the incoming stock symbols.

Abstract: A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19).

Abstract: A system and method for allowing a user to create instructions for building a packet processing integrated circuit. The system includes a user interface for allowing a user to define a desired packet processing algorithm (4) using a plurality of discrete packet processing blocks (22, 24, 28, 30), each of the blocks corresponding to a portion of the desired packet processing algorithm (4). The system allows the user to define connections (10) between the plurality of packet processing blocks (22, 24, 28, 30). The system processes a plurality of packet processing blocks (22, 24, 28, 30) and the connections to provide a list of instructions in a hardware description language for producing an integrated circuit capable of executing the desired packet processing algorithm (19).

Abstract: A System Packet Interface (SPI) level 4 receiver groups four consecutive 16 bit control/data words into a single 64 bit word (with a resultant rate of up to 210 MHz). The 64 bit word is processed for storage in a dual memory structure comprising two first-in-first-out (FIFO) memories for storing 64 bit words, wherein the 64 bit word may be stored in one, or both, of the FIFOs. The SPI-4.2 receiver issues commands that control subsequent processing of the 64 bit words (e.g., for alignment) using three types of commands, which are based on the relative temporal position of control words in the received data. Temporally, these commands are characterized as: PRE-COMMANDS, POST-COMMANDS and PRESENT-COMMANDS. A parallel general and selection method (PGSM) is used for FIFO Write Command Generation and for Diagonally Interleaved Parity (DIP-4) checking.